Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
- URL: http://arxiv.org/abs/2004.04706v1
- Date: Thu, 9 Apr 2020 17:40:10 GMT
- Title: Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
- Authors: Prakash Murali, Dripto M. Debroy, Kenneth R. Brown, Margaret Martonosi
- Abstract summary: Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware.
Current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture.
To progress towards the next major milestone of 50-100 qubits, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed.
- Score: 7.727277545143961
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: Trapped ions (TI) are a leading candidate for building Noisy
Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental
advantages over other technologies such as superconducting qubits, including
high qubit quality, coherence and connectivity. However, current TI systems are
small in size, with 5-20 qubits and typically use a single trap architecture
which has fundamental scalability limitations. To progress towards the next
major milestone of 50-100 qubits, a modular architecture termed the Quantum
Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device,
small traps are connected through ion shuttling. While the basic hardware
components for such devices have been demonstrated, building a 50-100 qubit
system is challenging because of a wide range of design possibilities for trap
sizing, communication topology and gate implementations and the need to match
diverse application resource requirements.
Towards realizing QCCD systems with 50-100 qubits, we perform an extensive
architectural study evaluating the key design choices of trap sizing,
communication topology and operation implementation methods. We built a design
toolflow which takes a QCCD architecture's parameters as input, along with a
set of applications and realistic hardware performance models. Our toolflow
maps the applications onto the target device and simulates their execution to
compute metrics such as application run time, reliability and device noise
rates. Using six applications and several hardware design points, we show that
trap sizing and communication topology choices can impact application
reliability by up to three orders of magnitude. Microarchitectural gate
implementation choices influence reliability by another order of magnitude.
From these studies, we provide concrete recommendations to tune these choices
to achieve highly reliable and performant application executions.
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