Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers

• URL: http://arxiv.org/abs/2004.04706v1
• Date: Thu, 9 Apr 2020 17:40:10 GMT
• Title: Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
• Authors: Prakash Murali, Dripto M. Debroy, Kenneth R. Brown, Margaret Martonosi
• Abstract summary: Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. Current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture. To progress towards the next major milestone of 50-100 qubits, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed.
• Score: 7.727277545143961
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubits, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements. Towards realizing QCCD systems with 50-100 qubits, we perform an extensive architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. We built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions.

Related papers

• Stacking the Odds: Full-Stack Quantum System Design Space Exploration [3.3595409695121656]
  We study the impact of layout methods, qubit routing techniques, compiler optimization levels, and hardware-specific properties.<n>Our simulations, though noisy, include quantum error correction (QEC) scenarios, revealing similar sensitivities to layout and connectivity.
  arXiv  Detail & Related papers  (2025-06-03T12:01:58Z)
• Near-Term Spin-Qubit Architecture Design via Multipartite Maximally-Entangled States [1.589509357008938]
  We introduce four metrics which ascertain the quality of genuine multipartite quantum entanglement, along with circuit-level fidelity measures. We devise simulations which combine expected hardware characteristics of spin-qubit devices with appropriate compilation techniques. We find that sparsely-connected spin-qubit lattices can approach comparable values of our metrics to those of the most highly-connected device architecture.
  arXiv  Detail & Related papers  (2024-12-17T12:55:40Z)
• Architectural Patterns for Designing Quantum Artificial Intelligence Systems [25.42535682546052]
  Utilising quantum computing technology to enhance artificial intelligence systems is expected to improve training and inference times, increase robustness against noise and adversarial attacks, and reduce the number of parameters without compromising accuracy. However, moving beyond proof-of-concept or simulations to develop practical applications of these systems faces significant challenges due to the limitations of quantum hardware and the underdeveloped knowledge base in software engineering for such systems.
  arXiv  Detail & Related papers  (2024-11-14T05:09:07Z)
• AsCAN: Asymmetric Convolution-Attention Networks for Efficient Recognition and Generation [48.82264764771652]
  We introduce AsCAN -- a hybrid architecture, combining both convolutional and transformer blocks. AsCAN supports a variety of tasks: recognition, segmentation, class-conditional image generation. We then scale the same architecture to solve a large-scale text-to-image task and show state-of-the-art performance.
  arXiv  Detail & Related papers  (2024-11-07T18:43:17Z)
• Quasar-ViT: Hardware-Oriented Quantization-Aware Architecture Search for Vision Transformers [56.37495946212932]
  Vision transformers (ViTs) have demonstrated their superior accuracy for computer vision tasks compared to convolutional neural networks (CNNs) This work proposes Quasar-ViT, a hardware-oriented quantization-aware architecture search framework for ViTs.
  arXiv  Detail & Related papers  (2024-07-25T16:35:46Z)
• Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
  We develop a reinforcement learning-based quantum compiler for a superconducting processor. We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths. Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
  arXiv  Detail & Related papers  (2024-06-18T01:49:48Z)
• Superconducting qubits at the utility scale: the potential and limitations of modularity [29.454068658181466]
  Fault-tolerant quantum computers (FTQCs) have the potential to address some of humanity's grand challenges.<n>This paper presents an architectural model of a potential FTQC based on superconducting qubits, divided into discrete modules and interconnected via coherent links.
  arXiv  Detail & Related papers  (2024-06-10T04:30:48Z)
• Multi-objective Differentiable Neural Architecture Search [58.67218773054753]
  We propose a novel NAS algorithm that encodes user preferences to trade-off performance and hardware metrics. Our method outperforms existing MOO NAS methods across a broad range of qualitatively different search spaces and datasets.
  arXiv  Detail & Related papers  (2024-02-28T10:09:04Z)
• Shuttling for Scalable Trapped-Ion Quantum Computers [2.8956730787977083]
  We propose an efficient shuttling schedule for Trapped-ion quantum computers. The proposed approach produces shuttling schedules with a close-to-minimal amount of time steps. An implementation of the proposed approach is publicly available as part of the open-source Munich Quantum Toolkit.
  arXiv  Detail & Related papers  (2024-02-21T19:00:04Z)
• An Architecture for Improved Surface Code Connectivity in Neutral Atoms [3.3186866268167146]
  We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's physical connectivity into a higher logical connectivity. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits.
  arXiv  Detail & Related papers  (2023-09-24T00:10:47Z)
• MAPLE-X: Latency Prediction with Explicit Microprocessor Prior Knowledge [87.41163540910854]
  Deep neural network (DNN) latency characterization is a time-consuming process. We propose MAPLE-X which extends MAPLE by incorporating explicit prior knowledge of hardware devices and DNN architecture latency.
  arXiv  Detail & Related papers  (2022-05-25T11:08:20Z)
• Scaling Quantum Approximate Optimization on Near-term Hardware [49.94954584453379]
  We quantify scaling of the expected resource requirements by optimized circuits for hardware architectures with varying levels of connectivity. We show the number of measurements, and hence total time to synthesizing solution, grows exponentially in problem size and problem graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.
  arXiv  Detail & Related papers  (2022-01-06T21:02:30Z)
• HELP: Hardware-Adaptive Efficient Latency Predictor for NAS via Meta-Learning [43.751220068642624]
  Hardware-adaptive Predictor (HELP) is a device-specific latency estimation problem as a meta-learning problem. We introduce novel hardware embeddings to embed any devices considering them as black-box functions that output latencies, and meta-learn the hardware-adaptive latency predictor in a device-dependent manner. We validate the proposed HELP for its latency estimation performance on unseen platforms, on which it achieves high estimation performance with as few as 10 measurement samples, outperforming all relevant baselines.
  arXiv  Detail & Related papers  (2021-06-16T08:36:21Z)
• Roadmap for Rare-earth Quantum Computing [42.0895440675898]
  Rare-earth ions in solids constitute one of the most versatile platforms for future quantum technology. One advantage is good coherence properties even when confined in strong natural traps inside a solid-state matrix. clusters of 50-100 single RE ions can act as high fidelity qubits in small processors.
  arXiv  Detail & Related papers  (2021-03-29T16:28:29Z)
• Interleaving: Modular architectures for fault-tolerant photonic quantum computing [50.591267188664666]
  Photonic fusion-based quantum computing (FBQC) uses low-loss photonic delays. We present a modular architecture for FBQC in which these components are combined to form "interleaving modules" Exploiting the multiplicative power of delays, each module can add thousands of physical qubits to the computational Hilbert space.
  arXiv  Detail & Related papers  (2021-03-15T18:00:06Z)
• Hardware-Centric AutoML for Mixed-Precision Quantization [34.39845532939529]
  Conventional quantization algorithm ignores the different hardware architectures and quantizes all the layers in a uniform way. In this paper, we introduce the Hardware-Aware Automated Quantization (HAQ) framework which leverages the reinforcement learning to automatically determine the quantization policy. Our framework effectively reduced the latency by 1.4-1.95x and the energy consumption by 1.9x with negligible loss of accuracy compared with the fixed bitwidth (8 bits) quantization.
  arXiv  Detail & Related papers  (2020-08-11T17:30:22Z)
• Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications [0.050789261636931045]
  Quantum computers with tens to hundreds of noisy qubits are being developed today. These near-term systems cannot simply be scaled-down non-error-corrected versions of future fault-tolerant large-scale quantum computers. We employ an application-system-qubit co-design methodology to architect a near-term quantum coprocessor.
  arXiv  Detail & Related papers  (2020-03-06T22:44:49Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.