Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization

• URL: http://arxiv.org/abs/2210.03916v1
• Date: Sat, 8 Oct 2022 05:00:26 GMT
• Title: Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization
• Abstract summary: Two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining.
• Score: 5.547686929207811
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.

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