HDCC: A Hyperdimensional Computing compiler for classification on
embedded systems and high-performance computing
- URL: http://arxiv.org/abs/2304.12398v1
- Date: Mon, 24 Apr 2023 19:16:03 GMT
- Title: HDCC: A Hyperdimensional Computing compiler for classification on
embedded systems and high-performance computing
- Authors: Pere Verg\'es, Mike Heddes, Igor Nunes, Tony Givargis, Alexandru
Nicolau
- Abstract summary: This work introduces the name compiler, the first open-source compiler that translates high-level descriptions of HDC classification methods into optimized C code.
name is designed like a modern compiler, featuring an intuitive and descriptive input language, an intermediate representation (IR), and a retargetable backend.
To substantiate these claims, we conducted experiments with HDCC on several of the most popular datasets in the HDC literature.
- Score: 58.720142291102135
- License: http://creativecommons.org/licenses/by-nc-sa/4.0/
- Abstract: Hyperdimensional Computing (HDC) is a bio-inspired computing framework that
has gained increasing attention, especially as a more efficient approach to
machine learning (ML). This work introduces the \name{} compiler, the first
open-source compiler that translates high-level descriptions of HDC
classification methods into optimized C code. The code generated by the
proposed compiler has three main features for embedded systems and
High-Performance Computing: (1) it is self-contained and has no library or
platform dependencies; (2) it supports multithreading and single instruction
multiple data (SIMD) instructions using C intrinsics; (3) it is optimized for
maximum performance and minimal memory usage. \name{} is designed like a modern
compiler, featuring an intuitive and descriptive input language, an
intermediate representation (IR), and a retargetable backend. This makes
\name{} a valuable tool for research and applications exploring HDC for
classification tasks on embedded systems and High-Performance Computing. To
substantiate these claims, we conducted experiments with HDCC on several of the
most popular datasets in the HDC literature. The experiments were run on four
different machines, including different hyperparameter configurations, and the
results were compared to a popular prototyping library built on PyTorch. The
results show a training and inference speedup of up to 132x, averaging 25x
across all datasets and machines. Regarding memory usage, using
10240-dimensional hypervectors, the average reduction was 5x, reaching up to
14x. When considering vectors of 64 dimensions, the average reduction was 85x,
with a maximum of 158x less memory utilization.
Related papers
- Register Your Forests: Decision Tree Ensemble Optimization by Explicit CPU Register Allocation [3.737361598712633]
We present a code generation approach for decision tree ensembles, which produces machine assembly code within a single conversion step.
The results show that the performance of decision tree ensemble inference can be significantly improved.
arXiv Detail & Related papers (2024-04-10T09:17:22Z) - INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order
Gradient Computations in Implicit Neural Representation Processing [66.00729477511219]
Given a function represented as a computation graph, traditional architectures face challenges in efficiently computing its nth-order gradient.
We introduce INR-Arch, a framework that transforms the computation graph of an nth-order gradient into a hardware-optimized dataflow architecture.
We present results that demonstrate 1.8-4.8x and 1.5-3.6x speedup compared to CPU and GPU baselines respectively.
arXiv Detail & Related papers (2023-08-11T04:24:39Z) - PowerFusion: A Tensor Compiler with Explicit Data Movement Description
and Instruction-level Graph IR [10.059491353103526]
We propose IntelliGen, a tensor compiler that can generate high-performance code for memory-intensive operators.
IntelliGen considers both computation and data movement optimizations.
We evaluate IntelliGen on NVIDIA GPU, AMD GPU, and Cambricon MLU, showing speedup up to 1.97x, 2.93x, and 16.91x (1.28x, 1.23x, and 2.31x on average)
arXiv Detail & Related papers (2023-07-11T03:17:40Z) - Evaluation of OpenAI Codex for HPC Parallel Programming Models Kernel
Generation [1.7646846505225735]
We evaluate AI-assisted generative capabilities on fundamental numerical kernels in high-performance computing.
We test the generated kernel codes for a variety of language-supported programming models.
We propose a proficiency metric around the initial 10 suggestions given for each prompt.
arXiv Detail & Related papers (2023-06-27T00:11:31Z) - Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architectures [67.47328776279204]
This work introduces a framework to develop efficient, portable Deep Learning and High Performance Computing kernels.
We decompose the kernel development in two steps: 1) Expressing the computational core using Processing Primitives (TPPs) and 2) Expressing the logical loops around TPPs in a high-level, declarative fashion.
We demonstrate the efficacy of our approach using standalone kernels and end-to-end workloads that outperform state-of-the-art implementations on diverse CPU platforms.
arXiv Detail & Related papers (2023-04-25T05:04:44Z) - An Extension to Basis-Hypervectors for Learning from Circular Data in
Hyperdimensional Computing [62.997667081978825]
Hyperdimensional Computing (HDC) is a computation framework based on properties of high-dimensional random spaces.
We present a study on basis-hypervector sets, which leads to practical contributions to HDC in general.
We introduce a method to learn from circular data, an important type of information never before addressed in machine learning with HDC.
arXiv Detail & Related papers (2022-05-16T18:04:55Z) - Understanding Hyperdimensional Computing for Parallel Single-Pass
Learning [47.82940409267635]
We show that HDC can outperform the state-of-the-art HDC model by up to 7.6% while maintaining hardware efficiency.
We propose a new class of VSAs, finite group VSAs, which surpass the limits of HDC.
Experimental results show that our RFF method and group VSA can both outperform the state-of-the-art HDC model by up to 7.6%.
arXiv Detail & Related papers (2022-02-10T02:38:56Z) - Brain-inspired Cognition in Next Generation Racetrack Memories [0.6850683267295249]
Hyperdimensional computing (HDC) is an emerging computational framework inspired by the brain that operates on vectors with thousands of dimensions to emulate cognition.
This paper presents an architecture based on racetrack memory (RTM) to conduct and accelerate the entire HDC framework within the memory.
The proposed solution requires minimal additional CMOS circuitry and uses a read operation across multiple domains in RTMs called transverse read (TR) to realize exclusive-or (XOR) and addition operations.
arXiv Detail & Related papers (2021-11-03T14:21:39Z) - PolyDL: Polyhedral Optimizations for Creation of High Performance DL
primitives [55.79741270235602]
We present compiler algorithms to automatically generate high performance implementations of Deep Learning primitives.
We develop novel data reuse analysis algorithms using the polyhedral model.
We also show that such a hybrid compiler plus a minimal library-use approach results in state-of-the-art performance.
arXiv Detail & Related papers (2020-06-02T06:44:09Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.