ChiPFormer: Transferable Chip Placement via Offline Decision Transformer
- URL: http://arxiv.org/abs/2306.14744v2
- Date: Tue, 1 Aug 2023 11:42:22 GMT
- Title: ChiPFormer: Transferable Chip Placement via Offline Decision Transformer
- Authors: Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, Ping Luo
- Abstract summary: reinforcement learning can improve human performance in chip placement.
ChiPFormer enables learning a transferable placement policy from fixed offline data.
ChiPFormer achieves significantly better placement quality while reducing the runtime by 10x.
- Score: 35.69382855465161
- License: http://creativecommons.org/licenses/by-nc-sa/4.0/
- Abstract: Placement is a critical step in modern chip design, aiming to determine the
positions of circuit modules on the chip canvas. Recent works have shown that
reinforcement learning (RL) can improve human performance in chip placement.
However, such an RL-based approach suffers from long training time and low
transfer ability in unseen chip circuits. To resolve these challenges, we cast
the chip placement as an offline RL formulation and present ChiPFormer that
enables learning a transferable placement policy from fixed offline data.
ChiPFormer has several advantages that prior arts do not have. First,
ChiPFormer can exploit offline placement designs to learn transferable policies
more efficiently in a multi-task setting. Second, ChiPFormer can promote
effective finetuning for unseen chip circuits, reducing the placement runtime
from hours to minutes. Third, extensive experiments on 32 chip circuits
demonstrate that ChiPFormer achieves significantly better placement quality
while reducing the runtime by 10x compared to recent state-of-the-art
approaches in both public benchmarks and realistic industrial tasks. The
deliverables are released at https://sites.google.com/view/chipformer/home.
Related papers
- ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation [7.660954005766763]
ChipAlign combines the strengths of a general instruction-aligned LLM with a chip-specific LLM.
ChipAlign significantly enhances instruction-following capabilities of existing chip LLMs.
arXiv Detail & Related papers (2024-12-15T04:21:24Z) - Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer [22.46061028295081]
reinforcement learning has emerged as a promising technique for improving placement quality.
Current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results.
We propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts.
We evaluate our approach on the ISPD 2005 and ICCAD 2015 benchmark, comparing the global half-perimeter wirelength and regularity of our proposed method against several competitive approaches.
arXiv Detail & Related papers (2024-12-10T04:01:21Z) - Policy Agnostic RL: Offline RL and Online RL Fine-Tuning of Any Class and Backbone [72.17534881026995]
We develop an offline and online fine-tuning approach called policy-agnostic RL (PA-RL)
We show the first result that successfully fine-tunes OpenVLA, a 7B generalist robot policy, autonomously with Cal-QL, an online RL fine-tuning algorithm.
arXiv Detail & Related papers (2024-12-09T17:28:03Z) - Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms [77.71341200638416]
ChiPBench is a benchmark designed to evaluate the effectiveness of AI-based chip placement algorithms.
We have gathered 20 circuits from various domains (e.g., CPU, GPU, and microcontrollers) for evaluation.
Results show that even if intermediate metric of a single-point algorithm is dominant, the final PPA results are unsatisfactory.
arXiv Detail & Related papers (2024-07-03T03:29:23Z) - Cost Explosion for Efficient Reinforcement Learning Optimisation of
Quantum Circuits [55.616364225463066]
Reinforcement Learning (RL) is a recent approach for learning strategies to optimise quantum circuits by increasing the reward of an optimisation agent.
Our goal is to improve the agent's optimization strategy, by including hints about how quantum circuits are optimized manually.
We show that allowing cost explosions offers significant advantages for RL training, such as reaching optimum circuits.
arXiv Detail & Related papers (2023-11-21T10:16:03Z) - MaskPlace: Fast Chip Placement via Reinforced Visual Representation
Learning [18.75057105112443]
This work presents MaskPlace to automatically generate a valid chip layout design within a few hours.
It recasts placement as a problem of learning pixel-level visual representation to comprehensively describe millions of modules on a chip.
It outperforms recent methods that represent a chip as a hypergraph.
arXiv Detail & Related papers (2022-11-24T02:22:09Z) - Routing and Placement of Macros using Deep Reinforcement Learning [0.0]
We train a model to place the nodes of a chip netlist onto a chip canvas.
We want to build a neural architecture that will accurately reward the agent across a wide variety of input netlist correctly.
arXiv Detail & Related papers (2022-05-19T02:40:58Z) - GDP: Stabilized Neural Network Pruning via Gates with Differentiable
Polarization [84.57695474130273]
Gate-based or importance-based pruning methods aim to remove channels whose importance is smallest.
GDP can be plugged before convolutional layers without bells and whistles, to control the on-and-off of each channel.
Experiments conducted over CIFAR-10 and ImageNet datasets show that the proposed GDP achieves the state-of-the-art performance.
arXiv Detail & Related papers (2021-09-06T03:17:10Z) - Chip Placement with Deep Reinforcement Learning [40.952111701288125]
We present a learning-based approach to chip placement.
Unlike prior methods, our approach has the ability to learn from past experience and improve over time.
In under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists.
arXiv Detail & Related papers (2020-04-22T17:56:07Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.