Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures

• URL: http://arxiv.org/abs/2307.05815v2
• Date: Fri, 07 Mar 2025 18:13:30 GMT
• Title: Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures
• Authors: Dipal Halder,
• Abstract summary: Research focuses on securing Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures.<n>Research builds on two methodologies: ObNoCs and POTENT.<n>New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The globalization of semiconductor supply chains has exposed Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures to critical security risks, including reverse engineering and IP theft. To address these threats, this work builds on two methodologies: ObNoCs [11], which obfuscates NoC topologies using programmable multiplexers, and POTENT [10], which enhances post-synthesis security against SAT-based attacks. These techniques ensure robust protection of NoC interconnects with minimal performance overhead. As the industry shifts to chiplet-based heterogeneous architectures, this research extends ObNoCs and POTENT to secure intra- and inter-chiplet interconnects. New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms. Experimental results demonstrate the practicality of these approaches for high-security applications, ensuring trust and reliability in monolithic and modular systems.

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