SPAIC: A sub-$\mu$W/Channel, 16-Channel General-Purpose Event-Based Analog Front-End with Dual-Mode Encoders

• URL: http://arxiv.org/abs/2309.03221v1
• Date: Thu, 31 Aug 2023 19:53:04 GMT
• Title: SPAIC: A sub-$\mu$W/Channel, 16-Channel General-Purpose Event-Based Analog Front-End with Dual-Mode Encoders
• Authors: Shyam Narayanan, Matteo Cartiglia, Arianna Rubino, Charles Lego, Charlotte Frenkel, Giacomo Indiveri
• Abstract summary: Low-power event-based analog front-ends are crucial to build efficient neuromorphic processing systems. We present a novel, highly analog front-end chip, denoted as SPAIC (signal-to-spike converter for analog AI computation) It offers a general-purpose dual-mode analog signal-to-spike encoding with delta modulation and pulse frequency modulation, with tunable frequency bands.
• Score: 6.6017549029623535
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Low-power event-based analog front-ends (AFE) are a crucial component required to build efficient end-to-end neuromorphic processing systems for edge computing. Although several neuromorphic chips have been developed for implementing spiking neural networks (SNNs) and solving a wide range of sensory processing tasks, there are only a few general-purpose analog front-end devices that can be used to convert analog sensory signals into spikes and interfaced to neuromorphic processors. In this work, we present a novel, highly configurable analog front-end chip, denoted as SPAIC (signal-to-spike converter for analog AI computation), that offers a general-purpose dual-mode analog signal-to-spike encoding with delta modulation and pulse frequency modulation, with tunable frequency bands. The ASIC is designed in a 180 nm process. It supports and encodes a wide variety of signals spanning 4 orders of magnitude in frequency, and provides an event-based output that is compatible with existing neuromorphic processors. We validated the ASIC for its functions and present initial silicon measurement results characterizing the basic building blocks of the chip.

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