CMOS-based Single-Cycle In-Memory XOR/XNOR

• URL: http://arxiv.org/abs/2310.18375v1
• Date: Thu, 26 Oct 2023 21:43:01 GMT
• Title: CMOS-based Single-Cycle In-Memory XOR/XNOR
• Authors: Shamiul Alam, Jack Hutchins, Nikhil Shukla, Kazi Asifuzzaman, Ahmedullah Aziz,
• Abstract summary: We propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2 times improvement in the latency compared with other existing CMOS-compatible solutions. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2 times improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.

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