Fully Randomized Pointers

• URL: http://arxiv.org/abs/2405.12513v2
• Date: Mon, 26 May 2025 03:01:16 GMT
• Title: Fully Randomized Pointers
• Authors: Sai Dhawal Phaye, Gregory J. Duck, Roland H. C. Yap, Trevor E. Carlson,
• Abstract summary: We propose Fully Randomized Pointers ( FRP) as a strong memory error defense that also maintains compatibility with existing binary software.<n>We show FRP is secure, practical, and compatible at the binary level, while our hardware implementation achieves low performance overheads.
• Score: 7.1754940591892735
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Memory errors continue to be a critical concern for programs written in low-level programming languages such as C and C++. Many different memory error defenses have been proposed, each with varying trade-offs in terms of overhead, compatibility, and attack resistance. Some defenses are highly compatible but only provide minimal protection, and can be easily bypassed by knowledgeable attackers. On the other end of the spectrum, capability systems offer very strong (unforgeable) protection, but require novel software and hardware implementations that are incompatible by definition. The challenge is to achieve both very strong protection and high compatibility. In this paper, we propose {\em Fully Randomized Pointers} FRP as a strong memory error defense that also maintains compatibility with existing binary software. The key idea behind FRP is to design a new pointer encoding scheme that allows for the full randomization of most pointer bits, rendering even brute force attacks impractical. We design a FRP encoding that is: (1) compatible with existing binary code (recompilation not needed); and (2) decoupled from the underlying object layout. FRP is prototyped as: (i) a software implementation (BlueFat) to test security and compatibility; and (ii) a proof-of-concept hardware implementation (GreenFat) to evaluate performance. We show FRP is secure, practical, and compatible at the binary level, while our hardware implementation achieves low performance overheads (< 4%).

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