SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine

• URL: http://arxiv.org/abs/2506.13983v1
• Date: Wed, 11 Jun 2025 06:43:24 GMT
• Title: SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
• Authors: Adarsh Gupta, Bhabesh Mali, Chandan Karfa,
• Abstract summary: This paper introduces SANGAM, a SystemVerilog Assertion Generation framework using LLM-guided Monte Carlo Tree Search for the automatic generation of SVAs from industry-level specifications.<n>The results demonstrated that our framework, SANGAM, can generate a robust set of SVAs, performing better in the evaluation process in comparison to the recent methods.
• Score: 0.5737287537823071
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Recent advancements in the field of reasoning using Large Language Models (LLMs) have created new possibilities for more complex and automatic Hardware Assertion Generation techniques. This paper introduces SANGAM, a SystemVerilog Assertion Generation framework using LLM-guided Monte Carlo Tree Search for the automatic generation of SVAs from industry-level specifications. The proposed framework utilizes a three-stage approach: Stage 1 consists of multi-modal Specification Processing using Signal Mapper, SPEC Analyzer, and Waveform Analyzer LLM Agents. Stage 2 consists of using the Monte Carlo Tree Self-Refine (MCTSr) algorithm for automatic reasoning about SVAs for each signal, and finally, Stage 3 combines the MCTSr-generated reasoning traces to generate SVA assertions for each signal. The results demonstrated that our framework, SANGAM, can generate a robust set of SVAs, performing better in the evaluation process in comparison to the recent methods.

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