Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads

• URL: http://arxiv.org/abs/2507.05556v1
• Date: Tue, 08 Jul 2025 00:38:44 GMT
• Title: Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
• Authors: Jumin Kim, Seungmin Baek, Minbok Wi, Hwayong Nam, Michael Jaemin Kim, Sukhan Lee, Kyomin Sohn, Jung Ho Ahn,
• Abstract summary: Per-Row Activation Counting (PRAC) modifies key DRAM timing parameters.<n>PRAC reportedly causes significant performance overheads in simulator-based studies.<n>We present the first real-machine performance analysis of PRAC.
• Score: 2.4012294360291477
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.

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