A Constant-Time Hardware Architecture for the CSIDH Key-Exchange Protocol

• URL: http://arxiv.org/abs/2508.11082v1
• Date: Thu, 14 Aug 2025 21:37:29 GMT
• Title: A Constant-Time Hardware Architecture for the CSIDH Key-Exchange Protocol
• Authors: Sina Bagheri, Masoud Kaveh, Francisco Hernando-Gallego, Diego Martín, Nuria Serrano,
• Abstract summary: This paper presents the first comprehensive hardware study of CSIDH on both FPGA and ASIC platforms.<n>The constant-time CSIDH-512 design requires $1.03times108$ clock cycles per key generation.<n>For ASIC implementation in a 180nm process, the design requires $1.065times108$ clock cycles and achieves a asciitilde 180 MHz frequency, resulting in a key generation latency of 591 ms.
• Score: 0.6597195879147555
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The commutative supersingular isogeny Diffie-Hellman (CSIDH) algorithm is a promising post-quantum key exchange protocol, notable for its exceptionally small key sizes, but hindered by computationally intensive key generation. Furthermore, practical implementations must operate in constant time to mitigate side-channel vulnerabilities, which presents an additional performance challenge. This paper presents, to our knowledge, the first comprehensive hardware study of CSIDH, establishing a performance baseline with a unified architecture on both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The architecture features a top-level finite state machine (FSM) that orchestrates a deeply pipelined arithmetic logic unit (ALU) to accelerate the underlying 512-bit finite field operations. The ALU employs a parallelized schoolbook multiplier, completing a 512$\times$512-bit multiplication in 22 clock cycles and enabling a full Montgomery modular multiplication in 87 cycles. The constant-time CSIDH-512 design requires $1.03\times10^{8}$ clock cycles per key generation. When implemented on a Xilinx Zynq UltraScale+ FPGA, the architecture achieves a 200 MHz clock frequency, corresponding to a 515 ms latency. For ASIC implementation in a 180nm process, the design requires $1.065\times10^{8}$ clock cycles and achieves a \textasciitilde 180 MHz frequency, resulting in a key generation latency of 591 ms. By providing the first public hardware performance metrics for CSIDH on both FPGA and ASIC platforms, this work delivers a crucial benchmark for future isogeny-based post-quantum cryptography (PQC) accelerators.

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