ARSP: Automated Repair of Verilog Designs via Semantic Partitioning

• URL: http://arxiv.org/abs/2508.16517v1
• Date: Fri, 22 Aug 2025 16:40:17 GMT
• Title: ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
• Abstract summary: ARSP is a two-stage system that mitigates dilution via semantics-guided fragmentation.<n>A synthetic data framework generates fragment-level training pairs spanning bug types, design styles, and scales to supervise both models.<n> Experiments show that ARSP 77.92% achieves pass@1 and 83.88% pass@5, outperforming mainstream commercial LLMs.
• Score: 34.51043089413753
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this effort, existing LLM-based automated debugging methods underperform on industrial-scale modules. A major reason for this is bug signal dilution in long contexts, where a few bug-relevant tokens are overwhelmed by hundreds of unrelated lines, diffusing the model's attention. To address this issue, we introduce ARSP, a two-stage system that mitigates dilution via semantics-guided fragmentation. A Partition LLM splits a module into semantically tight fragments; a Repair LLM patches each fragment; edits are merged without altering unrelated logic. A synthetic data framework generates fragment-level training pairs spanning bug types, design styles, and scales to supervise both models. Experiments show that ARSP achieves 77.92% pass@1 and 83.88% pass@5, outperforming mainstream commercial LLMs including Claude-3.7 and SOTA automated Verilog debugging tools Strider and MEIC. Also, semantic partitioning improves pass@1 by 11.6% and pass@5 by 10.2% over whole-module debugging, validating the effectiveness of fragment-level scope reduction in LLM-based Verilog debugging.

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