Platform Architecture for Tight Coupling of High-Performance Computing with Quantum Processors

• URL: http://arxiv.org/abs/2510.25213v2
• Date: Mon, 03 Nov 2025 02:15:53 GMT
• Title: Platform Architecture for Tight Coupling of High-Performance Computing with Quantum Processors
• Authors: Shane A. Caldwell, Moein Khazraee, Elena Agostini, Tom Lassiter, Corey Simpson, Omri Kahalon, Mrudula Kanuri, Jin-Sung Kim, Sam Stanwyck, Muyuan Li, Jan Olle, Christopher Chamberland, Ben Howe, Bruno Schmitt, Justin G. Lietz, Alex McCaskey, Jun Ye, Ang Li, Alicia B. Magann, Corey I. Ostrove, Kenneth Rudinger, Robin Blume-Kohout, Kevin Young, Nathan E. Miller, Yilun Xu, Gang Huang, Irfan Siddiqi, John Lange, Christopher Zimmer, Travis Humble,
• Abstract summary: NVQLink is an architecture for connecting high-performance computing resources to a quantum processing unit.<n>The network connecting the HPC and QSC is implemented relatively easily by QPU and QSC builders.
• Score: 13.07607004472821
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: We propose an architecture, called NVQLink, for connecting high-performance computing (HPC) resources to the control system of a quantum processing unit (QPU) to accelerate workloads necessary to the operation of the QPU. We aim to support every physical modality of QPU and every type of QPU system controller (QSC). The HPC resource is optimized for real-time (latency-bounded) processing on tasks with latency tolerances of tens of microseconds. The network connecting the HPC and QSC is implemented on commercially available Ethernet and can be adopted relatively easily by QPU and QSC builders, and we report a round-trip latency measurement of 3.96 microseconds (max) with prospects of further optimization. We describe an extension to the CUDA-Q programming model and runtime architecture to support real-time callbacks and data marshaling between the HPC and QSC. By doing so, NVQLink extends heterogeneous, kernel-based programming to the QSC, allowing the programmer to address CPU, GPU, and FPGA subsystems in the QSC, all in the same C++ program, avoiding the use of a performance-limiting HTTP interface. We provide a pattern for QSC builders to integrate with this architecture by making use of multi-level intermediate representation dialects and progressive lowering to encapsulate QSC code.

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