Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework

• URL: http://arxiv.org/abs/2511.06067v1
• Date: Sat, 08 Nov 2025 16:36:55 GMT
• Title: Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework
• Abstract summary: ArchCraft is a framework that converts architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification.<n>ArchCraft generates RTL and testbench code decoupled via symbols to facilitate verification and debug.<n>We systematically assess ArchCraft on Arch SynthBench, where the experiment results demonstrate the superiority of our proposed method.
• Score: 12.479447688005537
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware description languages (HDLs). To this end, we propose \textbf{ArchCraft}, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification. ArchCraft introduces a structured workflow, which uses formal graphs to capture the Architectural Blueprint and symbols to define the Functional Specification, translating unstructured academic papers into verifiable, hardware-aware designs. The framework then generates RTL and testbench (TB) code decoupled via these symbols to facilitate verification and debugging, ultimately reporting the circuit's Power, Area, and Performance (PPA). Moreover, we propose the first benchmark, \textbf{ArchSynthBench}, for synthesizing hardware from architectural descriptions, with a complete set of evaluation indicators, 50 project-level circuits, and around 600 circuit blocks. We systematically assess ArchCraft on ArchSynthBench, where the experiment results demonstrate the superiority of our proposed method, surpassing direct generation methods and the VerilogCoder framework in both paper understanding and code completion. Furthermore, evaluation and physical implementation of the generated executable RTL code show that these implementations meet all timing constraints without violations, and their performance metrics are consistent with those reported in the original papers.

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