FPGA-tailored algorithms for real-time decoding of quantum LDPC codes

• URL: http://arxiv.org/abs/2511.21660v1
• Date: Wed, 26 Nov 2025 18:33:47 GMT
• Title: FPGA-tailored algorithms for real-time decoding of quantum LDPC codes
• Authors: Satvik Maurya, Thilo Maurer, Markus Bühler, Drew Vandeth, Michael E. Beverland,
• Abstract summary: We analyze FPGA-tailored versions of three decoder classes for quantum low-density parity-check (qLDPC) codes.<n>For message passing, we analyze the recently introduced Relay decoder and its FPGA implementation.<n>For ordered statistics decoding, we introduce a filtered variant that concentrates on high-likelihood fault locations.<n>We design an FPGA-adapted generalized union-find decoder.
• Score: 1.213715600410032
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Real-time decoding is crucial for fault-tolerant quantum computing but likely requires specialized hardware such as field-programmable gate arrays (FPGAs), whose parallelism can alter relative algorithmic performance. We analyze FPGA-tailored versions of three decoder classes for quantum low-density parity-check (qLDPC) codes: message passing, ordered statistics, and clustering. For message passing, we analyze the recently introduced Relay decoder and its FPGA implementation; for ordered statistics decoding (OSD), we introduce a filtered variant that concentrates computation on high-likelihood fault locations; and for clustering, we design an FPGA-adapted generalized union-find decoder. We design a systolic algorithm for Gaussian elimination on rank-deficient systems that runs in linear parallel time, enabling fast validity checks and local corrections in clustering and eliminating costly full-rank inversion in filtered-OSD. Despite these improvements, both remain far slower and less accurate than Relay, suggesting message passing is the most viable route to real-time qLDPC decoding.

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