ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction

• URL: http://arxiv.org/abs/2511.23340v1
• Date: Fri, 28 Nov 2025 16:49:25 GMT
• Title: ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
• Authors: Bin Sun, Jingyi Zhou, Jianan Mu, Zhiteng Chao, Tianmeng Yang, Ziyue Xu, Jing Ye, Huawei Li,
• Abstract summary: In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing.<n>We propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists.<n>Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data.
• Score: 9.750084122633703
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.

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