Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval

• URL: http://arxiv.org/abs/2512.11690v1
• Date: Fri, 12 Dec 2025 16:12:02 GMT
• Title: Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
• Authors: Grant Bosworth, Keewoo Lee, Sunwoong Kim,
• Abstract summary: A plausible approach to protecting metadata is to have senders post messages on a public bulletin board and receivers scan it for relevant messages.<n>Oblivious message retrieval (OMR) leverages homomorphic encryption (HE) to improve user experience in this solution by delegating the scan to a resource-rich server.<n>This paper proposes a hardware architecture to accelerate the matrix-vector multiplication algorithm.
• Score: 2.8190885435355857
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: While end-to-end encryption protects the content of messages, it does not secure metadata, which exposes sender and receiver information through traffic analysis. A plausible approach to protecting this metadata is to have senders post encrypted messages on a public bulletin board and receivers scan it for relevant messages. Oblivious message retrieval (OMR) leverages homomorphic encryption (HE) to improve user experience in this solution by delegating the scan to a resource-rich server while preserving privacy. A key process in OMR is the homomorphic detection of pertinent messages for the receiver from the bulletin board. It relies on a specialized matrix-vector multiplication algorithm, which involves extensive multiplications between ciphertext vectors and plaintext matrices, as well as homomorphic rotations. The computationally intensive nature of this process limits the practicality of OMR. To address this challenge, this paper proposes a hardware architecture to accelerate the matrix-vector multiplication algorithm. The building homomorphic operators in this algorithm are implemented using high-level synthesis, with design parameters for different parallelism levels. These operators are then deployed on a field-programmable gate array platform using an efficient design space exploration strategy to accelerate homomorphic matrix-vector multiplication. Compared to a software implementation, the proposed hardware accelerator achieves a 13.86x speedup.

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