LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification

• URL: http://arxiv.org/abs/2601.02624v1
• Date: Tue, 06 Jan 2026 00:53:23 GMT
• Title: LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
• Authors: Md Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan, Nashmin Alam, Azim Uddin, Sujan Kumar Saha, Mark Tehranipoor, Farimah Farahmandi,
• Abstract summary: LAsset is a novel framework that identifies security assets from both hardware design specifications and register-transfer level (RTL) descriptions.<n>It achieves high classification accuracy, reaching up to 90% recall rate in system-on-chip (SoC) design, and 93% recall rate in IP designs.
• Score: 1.7639836127386677
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security verification of a hardware design is the identification of security assets, as it substantially influences downstream security verification tasks, such as threat modeling, security property generation, and vulnerability detection. Traditionally, assets are determined manually by security experts, requiring significant time and expertise. To address this challenge, we present LAsset, a novel automated framework that leverages large language models (LLMs) to identify security assets from both hardware design specifications and register-transfer level (RTL) descriptions. The framework performs structural and semantic analysis to identify intra-module primary and secondary assets and derives inter-module relationships to systematically characterize security dependencies at the design level. Experimental results show that the proposed framework achieves high classification accuracy, reaching up to 90% recall rate in SoC design, and 93% recall rate in IP designs. This automation in asset identification significantly reduces manual overhead and supports a scalable path forward for secure hardware development.

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