Surface code off-the-hook: diagonal syndrome-extraction scheduling

• URL: http://arxiv.org/abs/2602.09099v1
• Date: Mon, 09 Feb 2026 19:00:02 GMT
• Title: Surface code off-the-hook: diagonal syndrome-extraction scheduling
• Authors: Gilad Kishony, Austin Fowler,
• Abstract summary: Hook errors can reduce circuit-level code distance by a factor of two if the extraction schedule is poorly chosen.<n>Traditional approach uses N-shaped and Z-shaped schedules, selecting the orientation in each plaquette to avoid hook errors aligned with logical operators.<n>We propose the diagonal schedule, which orients hook errors along the diagonal of each plaquette.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: In the rotated surface code, hook errors (errors on auxiliary qubits midway through syndrome extraction that propagate to correlated two-qubit data errors) can reduce the circuit-level code distance by a factor of two if the extraction schedule is poorly chosen. The traditional approach uses N-shaped and Z-shaped schedules, selecting the orientation in each plaquette to avoid hook errors aligned with logical operators. However, this becomes increasingly complex within lattice surgery primitives with varied boundary geometries, and requires a 7-step schedule to avoid gate collisions. We propose the diagonal schedule, which orients hook errors along the diagonal of each plaquette. These diagonal errors crucially never align with logical operators regardless of boundary orientation, achieving full code distance. The diagonal schedule is globally uniform: all X-type plaquettes use one schedule and all Z-type plaquettes use another, eliminating geometry-dependent planning. On hardware supporting parallel measurement, reset, and gate operations, the schedule achieves a minimal period of 6 time steps, compared to 7 for the traditional approach. We demonstrate effectiveness for memory experiments, spatial junctions, spatial Hadamard gates, and patch rotation, showing equivalent or improved logical error rates while simplifying circuit construction.

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