QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

• URL: http://arxiv.org/abs/2603.14239v1
• Date: Sun, 15 Mar 2026 06:25:09 GMT
• Title: QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
• Abstract summary: We propose a data synthesis framework to tackle two challenges: the scarcity of high-quality real-world SVA corpora and the lack of reliable methods to determine NL-SVA semantic equivalence.<n>We train CodeV-SVA, a series of SVA generation models. Notably, CodeV-SVA achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1.
• Score: 41.09864485551356
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: SystemVerilog Assertions (SVAs) are crucial for hardware verification. Recent studies leverage general-purpose LLMs to translate natural language properties to SVAs (NL2SVA), but they perform poorly due to limited data. We propose a data synthesis framework to tackle two challenges: the scarcity of high-quality real-world SVA corpora and the lack of reliable methods to determine NL-SVA semantic equivalence. For the former, large-scale open-source RTLs are used to guide LLMs to generate real-world SVAs; for the latter, bidirectional translation serves as a data selection method. With the synthesized data, we train CodeV-SVA, a series of SVA generation models. Notably, CodeV-SVA-14B achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1, matching or exceeding advanced LLMs like GPT-5 and DeepSeek-R1.

Related papers

• HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification [10.931713427869598]
  We present HierSVA, an integrated suite that combines a pipeline, dataset, and benchmark for formal verification.<n>HierSVA-SP pairs an RTL preprocessing toolchain with an LLM-in-the-loop formal verification flow to produce reference SystemVerilog Assertions (SVA) on hierarchical RTL.<n>Applying it to BaseJump STL yields HierSVA-DS, a dataset of 342 modules, with hierarchy metadata and depths 0--9, accompanied by a deep subset of 28 module-bug pairs with natural-language specifications and bug variants.
  arXiv  Detail & Related papers  (2026-06-09T22:41:44Z)
• VL-JEPA: Joint Embedding Predictive Architecture for Vision-language [54.86811250366009]
  We introduce VL-JEPA, a vision-language model built on a Joint Embedding Predictive Architecture (JEPA)<n>By learning in an abstract representation space, the model focuses on task-relevant semantics while abstracting away surface-level linguistic variability.<n>At inference time, a lightweight text decoder is invoked only when needed to translate VL-JEPA predicted embeddings into text.
  arXiv  Detail & Related papers  (2025-12-11T18:59:22Z)
• Automated Snippet-Alignment Data Augmentation for Code Translation [51.59756295898321]
  parallel corpora can be categorized into program-alignment (PA) and snippet-alignment (SA) data.<n>We propose a data augmentation method that leverages LLMs to generate SA data automatically.<n>Experiments on TransCoder-test demonstrate that our augmented SA data combined with the two-stage training approach yields consistent improvements.
  arXiv  Detail & Related papers  (2025-10-16T02:30:24Z)
• Multimodal LLMs as Customized Reward Models for Text-to-Image Generation [60.164968941945645]
  We introduce LLaVA-Reward, an efficient reward model designed to automatically evaluate text-to-image (T2I) generations across multiple perspectives.<n>LLaVA-Reward directly utilizes the hidden states of multimodal large language models (MLLMs)<n>We train LLaVA-Reward on four evaluation perspectives: text-image alignment, fidelity/artifact, safety, and overall ranking.
  arXiv  Detail & Related papers  (2025-07-28T23:52:53Z)
• Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA [18.491764850064616]
  SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs.<n>Recent advances in large language models (LLMs) offer opportunities to automate this translation.<n>We propose a customized retrieval-augmented generation (RAG) framework and a synthetic fine-tuning dataset.
  arXiv  Detail & Related papers  (2025-06-12T17:52:06Z)
• QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation [51.393569044134445]
  Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification.<n> Extending RLVR to automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges.<n>We introduce CodeV-R1, an RLVR framework for training Verilog generation LLMs.
  arXiv  Detail & Related papers  (2025-05-30T03:51:06Z)
• ALLaVA: Harnessing GPT4V-Synthesized Data for Lite Vision-Language Models [45.040292339670096]
  Large vision-language models (LVLMs) have shown premise in a broad range of vision-language tasks with their strong reasoning and generalization capabilities. This study aims to bridge the performance gap between traditional-scale LVLMs and resource-friendly lite versions by adopting high-quality training data.
  arXiv  Detail & Related papers  (2024-02-18T19:26:49Z)
• Genixer: Empowering Multimodal Large Language Models as a Powerful Data Generator [63.762209407570715]
  Genixer is a comprehensive data generation pipeline consisting of four key steps. A synthetic VQA-like dataset trained with LLaVA1.5 enhances performance on 10 out of 12 multimodal benchmarks. MLLMs trained with task-specific datasets can surpass GPT-4V in generating complex instruction tuning data.
  arXiv  Detail & Related papers  (2023-12-11T09:44:41Z)
• Using LLMs to Facilitate Formal Verification of RTL [7.45362896000302]
  We show that GPT4 can generate correct SVA even for flawed RTL, without mirroring design errors. We extend the open-source AutoSVA framework by integrating our improved GPT4-based flow to generate safety properties.
  arXiv  Detail & Related papers  (2023-09-18T02:37:43Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.