Automatic Identification of Parallelizable Loops Using Transformer-Based Source Code Representations

• URL: http://arxiv.org/abs/2603.30040v1
• Date: Tue, 31 Mar 2026 17:54:27 GMT
• Title: Automatic Identification of Parallelizable Loops Using Transformer-Based Source Code Representations
• Abstract summary: We propose a Transformer-based approach to classify the parallelization potential of source code.<n>We adopt DistilBERT to process source code sequences using subword tokenization.<n>Results show consistently high performance, with mean accuracy above 99% and low false positive rates.
• Score: 1.5866931449827322
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Automatic parallelization remains a challenging problem in software engineering, particularly in identifying code regions where loops can be safely executed in parallel on modern multi-core architectures. Traditional static analysis techniques, such as dependence analysis and polyhedral models, often struggle with irregular or dynamically structured code. In this work, we propose a Transformer-based approach to classify the parallelization potential of source code, focusing on distinguishing independent (parallelizable) loops from undefined ones. We adopt DistilBERT to process source code sequences using subword tokenization, enabling the model to capture contextual syntactic and semantic patterns without handcrafted features. The approach is evaluated on a balanced dataset combining synthetically generated loops and manually annotated real-world code, using 10-fold cross-validation and multiple performance metrics. Results show consistently high performance, with mean accuracy above 99\% and low false positive rates, demonstrating robustness and reliability. Compared to prior token-based methods, the proposed approach simplifies preprocessing while improving generalization and maintaining computational efficiency. These findings highlight the potential of lightweight Transformer models for practical identification of parallelization opportunities at the loop level.

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