A Modular and T-Gate Efficient Architecture for Quantum Leading-Zero/One Counter

• URL: http://arxiv.org/abs/2604.13943v1
• Date: Wed, 15 Apr 2026 14:55:19 GMT
• Title: A Modular and T-Gate Efficient Architecture for Quantum Leading-Zero/One Counter
• Abstract summary: The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic.<n>We propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of conditional bit-flip operations.<n>Our design achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs.
• Score: 1.7423975970647592
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic, playing a critical role in normalization, floating-point units, dynamic range scaling, and logarithmic approximations. Conventional designs primarily rely on direct Boolean-to-quantum mapping, which results in inefficient resource utilization such as irregular gate growth and width-dependent resource overhead. In this work, we propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of systematic conditional bit-flip operations. Moreover, our design achieves functional polymorphism so that the same design can be easily toggled between zero and one detection, while ensuring seamless scalability to any bit-width without manual re-tuning. We further introduce a Parallel QLZOC (PQLZOC) variant and a Fan-Out optimized (FO-PQLZOC) design. In this work, we evaluate resource efficiency based on the classic criteria about T gates, including the number of total T gates being used (T-count) and the number of sequential T gate layers (T-depth). By exploiting the properties of all-zero/one qubit blocks and a hierarchical merge strategy, the proposed FO-PQLZOC reduces the T-depth from O(m) to O(log m), where m is the input size. Comparative analysis demonstrates that our optimized architecture achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs, providing a high-performance, T-gate efficient solution for general-purpose quantum arithmetic processors.

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