Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures

• URL: http://arxiv.org/abs/2604.18714v1
• Date: Mon, 20 Apr 2026 18:14:28 GMT
• Title: Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures
• Abstract summary: Quantum low-density parity-check codes offer superior encoding rates and large code distance compared to surface codes.<n>Long-range stabilizer measurements pose significant challenges for implementation on realistic hardware with limited connectivity.<n>We introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations.
• Score: 1.5531887595047786
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Quantum low-density parity-check codes are promising candidates towards scalable fault-tolerant quantum computation. Among these, bivariate bicycle (BB) codes offer superior encoding rates and large code distance compared to surface codes. However, their requirement on long-range stabilizer measurements poses significant challenges for implementation on realistic hardware with limited connectivity, such as superconducting circuit platforms. In this work, we introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations. Our approach utilizes a 2D toric network of oscillators as a flexible communication fabric linking qubits at each site. Such architecture significantly reduces the number of long-range couplers required from $O(n)$ to $O(\sqrt{n})$. Dual-rail qubits, along with native gates including Swap-Wait-Swap gates and beamsplitter SWAPs, ensure that long-range two-qubit gates can be executed with high fidelity and low latency. To further enhance performance, our qubit layout and routing algorithm utilize symmetries of the codes and enable maximum parallelism for long-range two-qubit gates, maintaining a low syndrome extraction cycle duration and scalability over the code length. We perform circuit-level simulation with realistic noise modeling based on experimental hardware parameters, observing an logical error rate per logical qubit per cycle of 3.06\% for $[[18, 4, 4]]$ BB code, 2.6$\times$ less than the existing experimental result. These findings provide a practical roadmap and identify key technological advancements needed to achieve low-overhead fault-tolerant quantum computing at scale.

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