Securing High-Performance Data Transfers: Implementing AES Encryption in RDMA Systems

• URL: http://arxiv.org/abs/2605.25026v1
• Date: Sun, 24 May 2026 12:06:22 GMT
• Title: Securing High-Performance Data Transfers: Implementing AES Encryption in RDMA Systems
• Abstract summary: This work explores the integration of RDMA and AES-128 encryption to secure data transfers without compromising performance.<n>We implement encryption directly within the data plane of a programmable Tofino switch using the P4 programming language.<n> Experimental results show that the system achieves throughput of 0.37 Gbps for 16-byte packets, 0.76 Gbps for 32-byte packets, 1.83 Gbps for 64-byte packets, and 1.9 Gbps for 128-byte packets.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Remote Direct Memory Access (RDMA) is a key enabler of high-performance systems, offering low latency, high throughput, and reduced CPU overhead by allowing direct memory-to-memory transfers between machines. However, its design bypasses traditional CPU-mediated security mechanisms, introducing critical vulnerabilities in untrusted environments. This work explores the integration of RDMA and AES-128 encryption to secure data transfers without compromising performance. We implement encryption directly within the data plane of a programmable Tofino switch using the P4 programming language. By offloading encryption from the CPU to the switch, our design preserves RDMA's performance benefits while addressing its security shortcomings. Experimental results show that the system achieves throughput of 0.37 Gbps for 16-byte packets, 0.76 Gbps for 32-byte packets, 1.83 Gbps for 64-byte packets, and 1.9 Gbps for 128-byte packets. These findings demonstrate the feasibility of secure, high-throughput RDMA communication using programmable network hardware.

Related papers

• PriSrv+: Privacy and Usability-Enhanced Wireless Service Discovery with Fast and Expressive Matchmaking Encryption [42.621633702087074]
  PriSrv+ is an advanced privacy and usability-enhanced service discovery protocol for modern wireless networks.<n>Key innovation in PriSrv+ is the development of Fast and Expressive Matchmaking Encryption (FEME)<n>PriSrv+ achieves superior performance, scalability, and efficiency compared to existing state-of-the-art protocols.
  arXiv  Detail & Related papers  (2026-06-04T09:07:19Z)
• Profiling-Driven Adaptive Distributed Transformer Inference on Embedded Edge Deployment [60.442064966340524]
  We present a prototype study on NVIDIA Jetson Orin Nano devices connected over WiFi.<n>Key finding is that the dominant bottleneck is not just network bandwidth but also the CPU- GPU staging during communication.<n>Experiments show that this strategy reduces latency by 65%-77% and energy consumption by 34%-52% relative to full-tensor exchange.
  arXiv  Detail & Related papers  (2026-05-25T10:39:28Z)
• CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing [2.1893572076171526]
  CryptoSRAM is a cryptographic architecture that performs operations directly within the MCU's standard array.<n>By repurposing the memory array into a massively parallel processing fabric, CryptoSRAM eliminates the data movement bottleneck.<n>For common cryptographic kernels, CryptoSRAM achieves throughput improvements of up to 74$times$ and 67$times$ for AES and SHA3, respectively.
  arXiv  Detail & Related papers  (2025-09-26T22:36:45Z)
• CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus [45.24207460381396]
  This paper presents a novel Intrusion Detection System (IDS) designed for the Controller Area Network (CAN) environment.<n>A RISC-V-based CAN receiver is simulated using the gem5 simulator, processing CAN frame payloads with AES-128 encryption as FreeRTOS tasks.<n>Results indicate that this approach could significantly improve CAN security and address emerging challenges in automotive cybersecurity.
  arXiv  Detail & Related papers  (2025-07-19T20:09:52Z)
• Toward a Lightweight, Scalable, and Parallel Secure Encryption Engine [0.0]
  SPiME is a lightweight, scalable, and FPGA-compatible Secure Processor-in-Memory Encryption architecture.<n>It integrates the Advanced Encryption Standard (AES-128) directly into a Processing-in-Memory framework.<n>It delivers over 25Gbps in sustained encryption throughput with predictable, low-latency performance.
  arXiv  Detail & Related papers  (2025-06-18T02:25:04Z)
• Lightweight, Secure and Stateful Serverless Computing with PSL [43.025002382616066]
  We present Function-as-a-Serivce (F) framework for Trusted Execution Environments (TEEs) The framework provides rich programming language support on heterogeneous TEE hardware for statically compiled binaries and/or WebAssembly (WASM) bytecodes. It achieves near-native execution speeds by utilizing the dynamic memory mapping capabilities of Intel SGX2.
  arXiv  Detail & Related papers  (2024-10-25T23:17:56Z)
• DeviceRadar: Online IoT Device Fingerprinting in ISPs using Programmable Switches [37.41464693677561]
  Device fingerprinting can be used by Internet Service Providers (ISPs) to identify vulnerable IoT devices for early prevention of threats. This paper proposes DeviceRadar, an online IoT device fingerprinting framework that achieves accurate, real-time processing in ISPs using programmable switches.
  arXiv  Detail & Related papers  (2024-04-19T09:31:11Z)
• Data-Oblivious ML Accelerators using Hardware Security Extensions [9.716425897388875]
  Outsourced computation can put client data confidentiality at risk. We develop Dolma, which applies DIFT to the Gemmini matrix multiplication accelerator. We show that Dolma incurs low overheads for large configurations.
  arXiv  Detail & Related papers  (2024-01-29T21:34:29Z)
• Physical Layer Encryption for Industrial Ethernet in Gigabit Optical Links [0.5624791703748108]
  New encryption method for high speed optical communications suitable for such kind of networks is proposed. New encryption method consists of a symmetric streaming encryption of the 8b/10b data flow at PCS (Physical Coding Sublayer) level.
  arXiv  Detail & Related papers  (2024-01-26T18:01:59Z)
• A high throughput Intrusion Detection System (IDS) to enhance the security of data transmission among research centers [39.65647745132031]
  This paper presents a packet sniffer that was designed using a commercial FPGA development board. The system can support a data throughput of 10 Gbit/s with preliminary results showing that the speed of data transmission can be reliably extended to 100 Gbit/s. It is particularly suited for the security of universities and research centers, where point-to-point network connections are dominant.
  arXiv  Detail & Related papers  (2023-11-10T14:30:00Z)
• SOCI^+: An Enhanced Toolkit for Secure OutsourcedComputation on Integers [50.608828039206365]
  We propose SOCI+ which significantly improves the performance of SOCI. SOCI+ employs a novel (2, 2)-threshold Paillier cryptosystem with fast encryption and decryption as its cryptographic primitive. Compared with SOCI, our experimental evaluation shows that SOCI+ is up to 5.4 times more efficient in computation and 40% less in communication overhead.
  arXiv  Detail & Related papers  (2023-09-27T05:19:32Z)
• Secure Video Streaming Using Dedicated Hardware [0.11470070927586014]
  The purpose of this article is to present a system that enhances the security, efficiency, and reconfigurability of an Internet-of-Things (IoT) system used for surveillance and monitoring.
  arXiv  Detail & Related papers  (2023-01-15T20:24:46Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.