ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities

• URL: http://arxiv.org/abs/2606.09915v1
• Date: Sat, 06 Jun 2026 15:36:41 GMT
• Title: ARTA: Adaptive Reinforcement-Learning-Based Throttling Agent for RowHammer Vulnerabilities
• Abstract summary: ARTA is a lightweight reinforcement-learning-based throttling mechanism that detects and suppresses RowHammer activity.<n> ARTA requires no DRAM-side hardware modification or offline training, using small structures in the memory controller.<n>Our evaluation shows that ARTA eliminates all bitflips at N_BO values down to 64, reduces bitflips up to 22K times at N_BO of 20, and improves performance up to 73.6% over state-of-the-art mitigation mechanisms.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: RowHammer vulnerability continues to intensify with DRAM scaling, reducing the activation threshold needed to induce bitflips and rendering existing defenses such as TRR, ECC, and refresh-based mechanisms vulnerable to sophisticated multi-bank hammering patterns. This work presents ARTA, a lightweight reinforcement-learning-based throttling mechanism that detects and suppresses RowHammer activity by monitoring fine-grained memory access behavior within the DRAM refresh window (t_REFW) and dynamically adjusting core throughput using a Q-learning frequency scaling governor. ARTA requires no DRAM-side hardware modification or offline training, using small SRAM structures in the memory controller -- a per-core, per-bank FIFO queue (CBF) and a compact Q-table -- for immediate deployment. Our evaluation shows that ARTA eliminates all bitflips at N_BO values down to 64, reduces bitflips up to 22K times at N_BO of 20, and improves performance up to 73.6% over state-of-the-art mitigation mechanisms by limiting preventive action overheads for improved memory bandwidth throughput. These results demonstrate that adaptive RL-based throttling provides robust, scalable, and high-performance RowHammer mitigation for emerging DRAM systems.

Related papers

• Hardware Mechanisms to Dynamically Throttle AI Performance [3.359978138010107]
  We introduce a set of microarchitecture knobs which dynamically control the available hardware resources to limit AI performance at runtime.<n>To minimize new logic and extra design cost, we build all four mechanisms from well-established microarchitectural primitives.<n>We show that these knobs achieve high performance sensitivity (up to 80% performance cut at 1/8 resource availability), negligible implementation cost (10K flip flops), fast stabilization after dynamic throttling (5-80K cycles), and minimal collateral impact on the rest of the chip.
  arXiv  Detail & Related papers  (2026-07-20T15:36:03Z)
• Training Large Reasoning Models Efficiently via Progressive Thought Encoding [63.254758972725654]
  Large reasoning models (LRMs) excel on complex problems but face a critical barrier to efficiency.<n>We introduce Progressive Thought, a parameter-efficient fine-tuning method that enables LRMs to reason effectively under fixed-size caches.
  arXiv  Detail & Related papers  (2026-02-18T20:03:38Z)
• MiniCPM-SALA: Hybridizing Sparse and Linear Attention for Efficient Long-Context Modeling [80.48332380100915]
  MiniCPM-SALA is a hybrid model that integrates the high-fidelity long-context modeling of sparse attention with the global efficiency of linear attention.<n>On a single NVIDIA A6000D GPU, the model achieves up to 3.5x the inference speed of the full-attention model at the sequence length of 256K tokens.
  arXiv  Detail & Related papers  (2026-02-12T09:37:05Z)
• $ρ$Hammer: Reviving RowHammer Attacks on New Architectures via Prefetching [37.49955872834092]
  Rowhammer is a critical vulnerability in dynamic random access memory (DRAM)<n>We present $rho$Hammer, a new Rowhammer framework that overcomes three core challenges impeding attacks on new architectures.<n>$rho$Hammer induces up to 200K+ additional bit flips within 2-hour attack pattern fuzzing processes and has a 112x higher flip rate than the load-based hammering baselines.
  arXiv  Detail & Related papers  (2025-10-18T15:40:53Z)
• ScaleWeaver: Weaving Efficient Controllable T2I Generation with Multi-Scale Reference Attention [86.93601565563954]
  ScaleWeaver is a framework designed to achieve high-fidelity, controllable generation upon advanced visual autoregressive( VAR) models.<n>The proposed Reference Attention module discards the unnecessary attention from image$rightarrow$condition, reducing computational cost.<n>Experiments show that ScaleWeaver delivers high-quality generation and precise control while attaining superior efficiency over diffusion-based methods.
  arXiv  Detail & Related papers  (2025-10-16T17:00:59Z)
• ARMOR: High-Performance Semi-Structured Pruning via Adaptive Matrix Factorization [99.96330641363396]
  ARMOR: (Adaptive Representation with Matrix-factORization) is a novel one-shot post-training pruning algorithm.<n>Instead of directly pruning weights, ARMOR factorizes each weight matrix into a 2:4 sparse core wrapped by two low-overhead, block diagonal matrices.<n>We demonstrate ARMOR consistently and significantly outperforms state-of-the-art 2:4 pruning methods across a wide range of downstream tasks and perplexity evaluations.
  arXiv  Detail & Related papers  (2025-10-07T02:39:20Z)
• In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning [59.091567092071564]
  In-memory training typically requires at least 8-bit conductance states to match digital baselines.<n>Many promising memristive devices such as ReRAM offer only about 4-bit resolution due to fabrication constraints.<n>This paper proposes a emphresidual learning framework that sequentially learns on multiple crossbar tiles to compensate the residual errors.
  arXiv  Detail & Related papers  (2025-10-02T19:44:25Z)
• Spark Transformer: Reactivating Sparsity in FFN and Attention [53.221448818147024]
  We introduce Spark Transformer, a novel architecture that achieves a high level of activation sparsity in both FFN and the attention mechanism.<n>This sparsity translates to a 2.5x reduction in FLOPs, leading to decoding wall-time speedups of up to 1.79x on CPU and 1.40x on GPU.
  arXiv  Detail & Related papers  (2025-06-07T03:51:13Z)
• Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions [6.157443107603247]
  RowHammer is a read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows)<n>With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads.<n>We present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips.<n>Our results show that Partial Charge Restoration for Aggressive Mitigation (PaCRAM) reduces the performance and energy overheads induced by five state-of-the-art RowHammer mitigation mechanisms with
  arXiv  Detail & Related papers  (2025-02-17T12:39:03Z)
• DAPPER: A Performance-Attack-Resilient Tracker for RowHammer Defense [1.1816942730023883]
  RowHammer vulnerabilities pose a significant threat to modern DRAM-based systems.<n>Perf-Attacks exploit shared structures to reduce DRAM bandwidth for co-running benign applications.<n>We propose secure hashing mechanisms to thwart adversarial attempts to capture the mapping of shared structures.
  arXiv  Detail & Related papers  (2025-01-31T02:38:53Z)
• Threshold Breaker: Can Counter-Based RowHammer Prevention Mechanisms Truly Safeguard DRAM? [8.973443004379561]
  This paper experimentally demonstrates a novel multi-sided fault injection attack technique called Threshold Breaker. It can effectively bypass the most advanced counter-based defense mechanisms by soft-attacking the rows at a farther physical distance from the target rows. As a case study, we compare the performance efficiency between our mechanism and a well-known double-sided attack by performing adversarial weight attacks on a modern Deep Neural Network (DNN)
  arXiv  Detail & Related papers  (2023-11-28T03:36:17Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.