Low-Cost Multi-Precision Systolic Arrays for Accelerating FHE NTTs on AI ASICs

• URL: http://arxiv.org/abs/2606.19866v1
• Date: Thu, 18 Jun 2026 07:26:13 GMT
• Title: Low-Cost Multi-Precision Systolic Arrays for Accelerating FHE NTTs on AI ASICs
• Abstract summary: Homomorphic Encryption (FHE) ensures robust data privacy but suffers from prohibitive computational overhead.<n>Accelerating FHE on AI hardware like Processing Units (TPUs) is promising, yet fundamentally limited by a precision mismatch.<n>We propose a minimally modified multi-precision systolic array that performs full-precision output reconstruction in sync with low-precision matrix multiplication.
• Score: 0.3186130813218338
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Fully Homomorphic Encryption (FHE) ensures robust data privacy but suffers from prohibitive computational overhead. Accelerating FHE on AI hardware like Tensor Processing Units (TPUs) is promising, yet fundamentally limited by a precision mismatch: TPUs are optimized for 8-bit arithmetic, whereas FHE and its critical parts such as the Number Theoretic Transform (NTT), demand high precision. Current approaches bridge this gap using matrix decomposition to execute NTT computations on low-precision matrix engines. However, reconstructing the full-precision results requires shift-and-add accumulation that does not match the dataflow of matrix multiplication. This forces offloading full-precision reconstruction from matrix engines to vector processors that disrupts the matrix multiplication dataflow, creating significant performance bottleneck. To resolve this limitation, we propose a minimally modified multi-precision systolic array that performs full-precision output reconstruction natively within the array in sync with low-precision matrix multiplication under a uniform dataflow. Synthesized at 7nm with OpenRoad, our design incurs negligible hardware overhead. Cycle-accurate simulations using SCALE-Sim demonstrate that natively executing NTTs on the proposed architecture achieves at least 1.33x speedup, for transform sizes 2^12 to 2^16 on 128x128 matrix engines, successfully enabling standard AI hardware to support high-precision FHE acceleration.

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