What Survives When You Compress a Recursive Reasoner for the Edge?
- URL: http://arxiv.org/abs/2606.26488v1
- Date: Thu, 25 Jun 2026 00:47:15 GMT
- Title: What Survives When You Compress a Recursive Reasoner for the Edge?
- Abstract summary: Recursive reasoning models can solve complex structured tasks with only a few million parameters by repeatedly updating a latent state.<n>We find that aggressive compression preserves local prediction but destroys global reasoning.<n>We introduce carry-trajectory fidelity, similarity to the full-precision reasoning path, as a label-free signal that predicts this damage and its recovery.
- Score: 15.460381731793975
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: Recursive reasoning models can solve complex structured tasks with only a few million parameters by repeatedly updating a latent state. Deploying these models on edge hardware requires significant compression, but unlike conventional sequence models, quantization errors compound across recursive reasoning cycles rather than across output tokens. As a result, standard intuitions about compression fail to apply. In this work, we ask what survives when recursive reasoners are compressed. Across a full precision sweep, three tasks, and two recursive architectures, we find that aggressive compression preserves local prediction but destroys global reasoning: cell accuracy holds while puzzle-exact accuracy collapses to zero under naive INT4 pruning, distillation, and linear attention alike. Token-level objectives, including quantization-aware training, cannot repair it. The collapse is architectural -- it strikes MLP-mixing recursion but not attention on the same task -- and we reverse it with per-channel calibrated INT4 without retraining. We also introduce carry-trajectory fidelity, the cosine similarity to the full-precision reasoning path, as a label-free signal that predicts this damage and its recovery before a task evaluation. The combined result is a deployment recipe: flash-streamed embeddings remove a 99.4MB bottleneck, INT8 at one cycle matches full-depth accuracy at 6x fewer FLOPs (8MB SoC), and calibrated INT4 fits a 4MB microcontroller.
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