Scalable Circuit Cutting: A Framework for Combined Gate and Wire Cuts Using Gate Groups

• URL: http://arxiv.org/abs/2608.05287v1
• Date: Wed, 05 Aug 2026 18:00:03 GMT
• Title: Scalable Circuit Cutting: A Framework for Combined Gate and Wire Cuts Using Gate Groups
• Abstract summary: This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy.<n>By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits.
• Score: 4.494265705354169
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.

Related papers

• Sparse Attention Post-Training for Mechanistic Interpretability [55.030850996535776]
  We introduce a simple post-training method that makes transformer attention sparse without sacrificing performance.<n>Applying a flexible sparsity regularisation under a constrained-loss objective, we show on models up to 1B parameters that it is possible to retain the original pretraining loss while reducing attention connectivity to $approx 0.3 % of its edges.
  arXiv  Detail & Related papers  (2025-12-05T16:40:08Z)
• Circuit cutting with classical side information [1.3791394805787949]
  We provide a formalization of general circuit cutting techniques utilizing side information through quantum instruments.<n>We find that in certain scenarios, side information does not yield any reduction in sampling overhead, whereas in others it is essential for circuit cutting to be feasible at all.
  arXiv  Detail & Related papers  (2025-03-28T12:43:34Z)
• Position-aware Automatic Circuit Discovery [59.64762573617173]
  We identify a gap in existing circuit discovery methods, treating model components as equally relevant across input positions.<n>We propose two improvements to incorporate positionality into circuits, even on tasks containing variable-length examples.<n>Our approach enables fully automated discovery of position-sensitive circuits, yielding better trade-offs between circuit size and faithfulness compared to prior work.
  arXiv  Detail & Related papers  (2025-02-07T00:18:20Z)
• A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit Knitting [0.9968037829925942]
  Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware. We propose a hardware-aware framework aiming to advance the practicability of circuit knitting. We show that our framework reduces total subcircuits depth by up to 64% (48% on average) compared to the state-of-the-art approach.
  arXiv  Detail & Related papers  (2024-09-05T19:18:30Z)
• Finding Transformer Circuits with Edge Pruning [71.12127707678961]
  We propose Edge Pruning as an effective and scalable solution to automated circuit discovery.<n>Our method finds circuits in GPT-2 that use less than half the number of edges compared to circuits found by previous methods.<n>Thanks to its efficiency, we scale Edge Pruning to CodeLlama-13B, a model over 100x the scale that prior methods operate on.
  arXiv  Detail & Related papers  (2024-06-24T16:40:54Z)
• Cutting circuits with multiple two-qubit unitaries [1.3791394805787949]
  We derive a formula for the optimal sampling overhead for cutting an arbitrary number of two-qubit unitaries.<n>We find that cutting several arbitrary two-qubit unitaries together is cheaper than cutting them individually.
  arXiv  Detail & Related papers  (2023-12-18T19:00:07Z)
• Circuit Cutting with Non-Maximally Entangled States [59.11160990637615]
  Distributed quantum computing combines the computational power of multiple devices to overcome the limitations of individual devices. circuit cutting techniques enable the distribution of quantum computations through classical communication. Quantum teleportation allows the distribution of quantum computations without an exponential increase in shots. We propose a novel circuit cutting technique that leverages non-maximally entangled qubit pairs.
  arXiv  Detail & Related papers  (2023-06-21T08:03:34Z)
• All this for one qubit? Bounds on local circuit cutting schemes [0.0]
  We show that a locally-acting circuit cutting scheme can efficiently partition even a single qubit from the rest of a circuit. We also show that any (local or otherwise) circuit cutting scheme cannot function by only applying unital channels.
  arXiv  Detail & Related papers  (2023-03-23T16:44:38Z)
• Optimal wire cutting with classical communication [3.577310844634503]
  We show that the optimal cost for cutting wires without and with classical communication between the subcircuits scales as $O(16n)$ and $O(4n)$, respectively.
  arXiv  Detail & Related papers  (2023-02-07T10:19:58Z)
• Software mitigation of coherent two-qubit gate errors [55.878249096379804]
  Two-qubit gates are important components of quantum computing. But unwanted interactions between qubits (so-called parasitic gates) can degrade the performance of quantum applications. We present two software methods to mitigate parasitic two-qubit gate errors.
  arXiv  Detail & Related papers  (2021-11-08T17:37:27Z)
• On the realistic worst case analysis of quantum arithmetic circuits [69.43216268165402]
  We show that commonly held intuitions when designing quantum circuits can be misleading. We show that reducing the T-count can increase the total depth. We illustrate our method on addition and multiplication circuits using ripple-carry.
  arXiv  Detail & Related papers  (2021-01-12T21:36:16Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.