RANC: Reconfigurable Architecture for Neuromorphic Computing

• URL: http://arxiv.org/abs/2011.00624v1
• Date: Sun, 1 Nov 2020 20:29:52 GMT
• Title: RANC: Reconfigurable Architecture for Neuromorphic Computing
• Authors: Joshua Mack, Ruben Purdy, Kris Rockowitz, Michael Inouye, Edward Richter, Spencer Valancius, Nirmal Kumbhare, Md Sahil Hassan, Kaitlin Fair, John Mixter, Ali Akoglu
• Abstract summary: We present RANC: a Reconfigurable Architecture for Neuromorphic Computing. RANC enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We show the utility of the RANC ecosystem by showing its ability to recreate behavior of the IBM's TrueNorth. We demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.
• Score: 1.1534748916340396
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Neuromorphic architectures have been introduced as platforms for energy efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from non-machine learning application domains. In order to lift the barriers to entry for hardware designers and application developers we present RANC: a Reconfigurable Architecture for Neuromorphic Computing, an open-source highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of the IBM's TrueNorth and validate with direct comparison to IBM's Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of Synthetic Aperture Radar classification and Vector Matrix Multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.

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