A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses

• URL: http://arxiv.org/abs/2012.02695v1
• Date: Fri, 4 Dec 2020 16:04:32 GMT
• Title: A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses
• Authors: Ramtin Zand
• Abstract summary: MRAM devices are leveraged to realize sigmoidal neurons and binarized synapses for a single-cycle analog in-memory computing architecture. An analog SOT-MRAM-based neuron bitcell is proposed which achieves a 12x reduction in power-area-product. An analog IMC architecture achieves at least two and four orders of magnitude performance improvement compared to a mixed-signal analog/digital IMC architecture.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: In this paper, spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) devices are leveraged to realize sigmoidal neurons and binarized synapses for a single-cycle analog in-memory computing (IMC) architecture. First, an analog SOT-MRAM-based neuron bitcell is proposed which achieves a 12x reduction in power-area-product compared to the previous most power- and area-efficient analog sigmoidal neuron design. Next, proposed neuron and synapse bit cells are used within memory subarrays to form an analog IMC-based multilayer perceptron (MLP) architecture for the MNIST pattern recognition application. The architecture-level results exhibit that our analog IMC architecture achieves at least two and four orders of magnitude performance improvement compared to a mixed-signal analog/digital IMC architecture and a digital GPU implementation, respectively while realizing a comparable classification accuracy.

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