GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN
Accelerator Chip at the Speed of 318FPS
- URL: http://arxiv.org/abs/2101.10444v1
- Date: Sat, 9 Jan 2021 23:11:48 GMT
- Title: GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN
Accelerator Chip at the Speed of 318FPS
- Abstract summary: We propose the integer encoding for the mask of the GnetSeg model, which minimizes the latency of data transfer between the CNN accelerator and the host CPU.
Experiment shows that the model running on the 224mW chip achieves the speed of 318FPS with excellent accuracy for applications such as person segmentation.
- Score: 7.78162383358657
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: Semantic segmentation is the task to cluster pixels on an image belonging to
the same class. It is widely used in the real-world applications including
autonomous driving, medical imaging analysis, industrial inspection, smartphone
camera for person segmentation and so on. Accelerating the semantic
segmentation models on the mobile and edge devices are practical needs for the
industry. Recent years have witnessed the wide availability of CNN
(Convolutional Neural Networks) accelerators. They have the advantages on power
efficiency, inference speed, which are ideal for accelerating the semantic
segmentation models on the edge devices. However, the CNN accelerator chips
also have the limitations on flexibility and memory. In addition, the CPU load
is very critical because the CNN accelerator chip works as a co-processor with
a host CPU. In this paper, we optimize the semantic segmentation model in order
to fully utilize the limited memory and the supported operators on the CNN
accelerator chips, and at the same time reduce the CPU load of the CNN model to
zero. The resulting model is called GnetSeg. Furthermore, we propose the
integer encoding for the mask of the GnetSeg model, which minimizes the latency
of data transfer between the CNN accelerator and the host CPU. The experimental
result shows that the model running on the 224mW chip achieves the speed of
318FPS with excellent accuracy for applications such as person segmentation.
Related papers
- DPU or GPU for Accelerating Neural Networks Inference -- Why not both? Split CNN Inference [0.0]
partitioning CNN inference across DPU and GPU (Split CNN Inference) is proposed.<n>GNN-based partition index prediction method is proposed to automate the partitioning of CNNs needed for the Split Inference.<n>Results demonstrate up to 2.48x latency improvement over DPU-only execution and up to 3.37x over GPU-only execution.
arXiv Detail & Related papers (2026-04-30T19:49:55Z) - CNN Mixture-of-Depths [4.150676163661315]
Mixture-of-Depths (MoD) for Convolutional Neural Networks (CNNs)
We introduce Mixture-of-Depths (MoD) for Convolutional Neural Networks (CNNs)
arXiv Detail & Related papers (2024-09-25T15:19:04Z) - OA-CNNs: Omni-Adaptive Sparse CNNs for 3D Semantic Segmentation [70.17681136234202]
We reexamine the design distinctions and test the limits of what a sparse CNN can achieve.
We propose two key components, i.e., adaptive receptive fields (spatially) and adaptive relation, to bridge the gap.
This exploration led to the creation of Omni-Adaptive 3D CNNs (OA-CNNs), a family of networks that integrates a lightweight module.
arXiv Detail & Related papers (2024-03-21T14:06:38Z) - SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast,
Energy-Efficient Inference of Integer-Quantized CNNs [0.0]
A CNN inference task uses convolution operations that are typically transformed into vector-dot-product (VDP) operations.
Several photonic microring resonators (MRRs) based hardware architectures have been proposed to accelerate integer-quantized CNNs.
Existing photonic MRR-based analog accelerators exhibit a very strong trade-off between the achievable input/weight precision and VDP operation size.
arXiv Detail & Related papers (2023-02-14T13:35:15Z) - Scaling Up Your Kernels to 31x31: Revisiting Large Kernel Design in CNNs [148.0476219278875]
We revisit large kernel design in modern convolutional neural networks (CNNs)
Inspired by recent advances of vision transformers (ViTs), in this paper, we demonstrate that using a few large convolutional kernels instead of a stack of small kernels could be a more powerful paradigm.
We propose RepLKNet, a pure CNN architecture whose kernel size is as large as 31x31, in contrast to commonly used 3x3.
arXiv Detail & Related papers (2022-03-13T17:22:44Z) - Continual 3D Convolutional Neural Networks for Real-time Processing of
Videos [93.73198973454944]
We introduce Continual 3D Contemporalal Neural Networks (Co3D CNNs)
Co3D CNNs process videos frame-by-frame rather than by clip by clip.
We show that Co3D CNNs initialised on the weights from preexisting state-of-the-art video recognition models reduce floating point operations for frame-wise computations by 10.0-12.4x while improving accuracy on Kinetics-400 by 2.3-3.8x.
arXiv Detail & Related papers (2021-05-31T18:30:52Z) - A Joint Energy and Latency Framework for Transfer Learning over 5G
Industrial Edge Networks [53.26338041079138]
We propose a transfer learning-enabled edge-CNN framework for 5G industrial edge networks.
In particular, the edge server can use the existing image dataset to train the CNN in advance.
With the aid of TL, the devices that are not participating in the training only need to fine-tune the trained edge-CNN model without training from scratch.
arXiv Detail & Related papers (2021-04-19T15:13:16Z) - MoViNets: Mobile Video Networks for Efficient Video Recognition [52.49314494202433]
3D convolutional neural networks (CNNs) are accurate at video recognition but require large computation and memory budgets.
We propose a three-step approach to improve computational efficiency while substantially reducing the peak memory usage of 3D CNNs.
arXiv Detail & Related papers (2021-03-21T23:06:38Z) - GnetDet: Object Detection Optimized on a 224mW CNN Accelerator Chip at
the Speed of 106FPS [10.644839299403612]
We optimize the object detection model on a CNN accelerator chip by minimizing the CPU load.
The experimental result shows that the GnetDet model running on a 224mW chip achieves the speed of 106FPS with excellent accuracy.
arXiv Detail & Related papers (2021-02-19T06:16:42Z) - RT3D: Achieving Real-Time Execution of 3D Convolutional Neural Networks
on Mobile Devices [57.877112704841366]
This paper proposes RT3D, a model compression and mobile acceleration framework for 3D CNNs.
For the first time, real-time execution of 3D CNNs is achieved on off-the-shelf mobiles.
arXiv Detail & Related papers (2020-07-20T02:05:32Z) - ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network [0.0]
This thesis explores the potential of FPGA-based CNN acceleration.
It demonstrates a fully functional proof-of-concept CNN implementation on a Zynq System-on-Chip.
arXiv Detail & Related papers (2020-05-14T11:54:04Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.