Characterizing Concurrency Mechanisms for NVIDIA GPUs under Deep
Learning Workloads
- URL: http://arxiv.org/abs/2110.00459v1
- Date: Fri, 1 Oct 2021 14:48:50 GMT
- Title: Characterizing Concurrency Mechanisms for NVIDIA GPUs under Deep
Learning Workloads
- Authors: Guin Gilman and Robert J. Walls
- Abstract summary: We investigate the performance of the mechanisms available on NVIDIA's new Ampere GPU microarchitecture under deep learning and inference workloads.
We find that the lack of fine-grained preemption mechanisms, robust task prioritization options, and contention-aware thread block placement policies limits the effectiveness of NVIDIA's mechanisms.
- Score: 1.0660480034605242
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: We investigate the performance of the concurrency mechanisms available on
NVIDIA's new Ampere GPU microarchitecture under deep learning training and
inference workloads. In contrast to previous studies that treat the GPU as a
black box, we examine scheduling at the microarchitectural level. We find that
the lack of fine-grained preemption mechanisms, robust task prioritization
options, and contention-aware thread block placement policies limits the
effectiveness of NVIDIA's concurrency mechanisms. In summary, the sequential
nature of deep learning workloads and their fluctuating resource requirements
and kernel runtimes make executing such workloads while maintaining
consistently high utilization and low, predictable turnaround times difficult
on current NVIDIA hardware.
Related papers
- NGPU-LM: GPU-Accelerated N-Gram Language Model for Context-Biasing in Greedy ASR Decoding [54.88765757043535]
This work rethinks data structures for statistical n-gram language models to enable fast and parallel operations for GPU-optimized inference.<n>Our approach, named NGPU-LM, introduces customizable greedy decoding for all major ASR model types with less than 7% computational overhead.<n>The proposed approach can eliminate more than 50% of the accuracy gap between greedy and beam search for out-of-domain scenarios while avoiding significant slowdown caused by beam search.
arXiv Detail & Related papers (2025-05-28T20:43:10Z) - SGPRS: Seamless GPU Partitioning Real-Time Scheduler for Periodic Deep Learning Workloads [0.9898607871253774]
We propose SGPRS, the first real-time GPU scheduler considering zero configuration partition switch.
The proposed scheduler not only meets more deadlines for parallel tasks but also sustains overall performance beyond the pivot point.
arXiv Detail & Related papers (2024-04-13T18:29:26Z) - FIKIT: Priority-Based Real-time GPU Multi-tasking Scheduling with Kernel
Identification [2.9271819018953162]
In a cloud computing cluster, serving a GPU's computation power through multi-tasks sharing is highly demanded.
Existing GPU sharing solutions focus on reducing task-level waiting time or task-level switching costs when multiple jobs competing for a single GPU.
We present a novel kernel-level scheduling strategy called FIKIT: Filling Inter- Kernel Idle Time.
arXiv Detail & Related papers (2023-11-17T07:25:18Z) - FusionAI: Decentralized Training and Deploying LLMs with Massive
Consumer-Level GPUs [57.12856172329322]
We envision a decentralized system unlocking the potential vast untapped consumer-level GPU.
This system faces critical challenges, including limited CPU and GPU memory, low network bandwidth, the variability of peer and device heterogeneity.
arXiv Detail & Related papers (2023-09-03T13:27:56Z) - Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architectures [67.47328776279204]
This work introduces a framework to develop efficient, portable Deep Learning and High Performance Computing kernels.
We decompose the kernel development in two steps: 1) Expressing the computational core using Processing Primitives (TPPs) and 2) Expressing the logical loops around TPPs in a high-level, declarative fashion.
We demonstrate the efficacy of our approach using standalone kernels and end-to-end workloads that outperform state-of-the-art implementations on diverse CPU platforms.
arXiv Detail & Related papers (2023-04-25T05:04:44Z) - A High-Performance Accelerator for Super-Resolution Processing on
Embedded GPU [24.084304913250826]
We implement a full-stack SR acceleration framework on embedded devices.
The communication and computation bottlenecks in the deep dictionary learning-based SR models are tackled perfectly.
arXiv Detail & Related papers (2023-03-16T00:09:09Z) - Intelligence Processing Units Accelerate Neuromorphic Learning [52.952192990802345]
Spiking neural networks (SNNs) have achieved orders of magnitude improvement in terms of energy consumption and latency.
We present an IPU-optimized release of our custom SNN Python package, snnTorch.
arXiv Detail & Related papers (2022-11-19T15:44:08Z) - Towards making the most of NLP-based device mapping optimization for
OpenCL kernels [5.6596607119831575]
We extend the work of Cummins et al., namely Deeptune, that tackles the problem of optimal device selection ( CPU or GPU) for accelerated OpenCL kernels.
We propose four different models that provide enhanced contextual information of source codes.
Experimental results show that our proposed methodology surpasses that of Cummins et al. work, providing up to 4% improvement in prediction accuracy.
arXiv Detail & Related papers (2022-08-30T10:20:55Z) - GPU-Accelerated Machine Learning in Non-Orthogonal Multiple Access [71.58925117604039]
Non-orthogonal multiple access (NOMA) is an interesting technology that enables massive connectivity as required in future 5G and 6G networks.
We propose a neural network architecture that combines the advantages of both linear and non-linear processing.
arXiv Detail & Related papers (2022-06-13T09:38:23Z) - MPLP++: Fast, Parallel Dual Block-Coordinate Ascent for Dense Graphical
Models [96.1052289276254]
This work introduces a new MAP-solver, based on the popular Dual Block-Coordinate Ascent principle.
Surprisingly, by making a small change to the low-performing solver, we derive the new solver MPLP++ that significantly outperforms all existing solvers by a large margin.
arXiv Detail & Related papers (2020-04-16T16:20:53Z) - Faster than FAST: GPU-Accelerated Frontend for High-Speed VIO [46.20949184826173]
This work focuses on the applicability of efficient low-level, GPU hardware-specific instructions to improve on existing computer vision algorithms.
Especially non-maxima suppression and the subsequent feature selection are prominent contributors to the overall image processing latency.
arXiv Detail & Related papers (2020-03-30T14:16:23Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.