Silicon photonic subspace neural chip for hardware-efficient deep
learning
- URL: http://arxiv.org/abs/2111.06705v1
- Date: Thu, 11 Nov 2021 06:34:05 GMT
- Title: Silicon photonic subspace neural chip for hardware-efficient deep
learning
- Authors: Chenghao Feng, Jiaqi Gu, Hanqing Zhu, Zhoufeng Ying, Zheng Zhao, David
Z. Pan and Ray T. Chen
- Abstract summary: optical neural network (ONN) is a promising candidate for next-generation neurocomputing.
We devise a hardware-efficient photonic subspace neural network architecture.
We experimentally demonstrate our PSNN on a butterfly-style programmable silicon photonic integrated circuit.
- Score: 11.374005508708995
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: As deep learning has shown revolutionary performance in many artificial
intelligence applications, its escalating computation demand requires hardware
accelerators for massive parallelism and improved throughput. The optical
neural network (ONN) is a promising candidate for next-generation
neurocomputing due to its high parallelism, low latency, and low energy
consumption. Here, we devise a hardware-efficient photonic subspace neural
network (PSNN) architecture, which targets lower optical component usage, area
cost, and energy consumption than previous ONN architectures with comparable
task performance. Additionally, a hardware-aware training framework is provided
to minimize the required device programming precision, lessen the chip area,
and boost the noise robustness. We experimentally demonstrate our PSNN on a
butterfly-style programmable silicon photonic integrated circuit and show its
utility in practical image recognition tasks.
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