A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning

• URL: http://arxiv.org/abs/2207.00336v1
• Date: Fri, 1 Jul 2022 11:04:53 GMT
• Title: A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning
• Authors: Yiwen Liao, Bin Yang, Rapha\"el Latty, Jochen Rivoir
• Abstract summary: In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. We leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.
• Score: 5.904240881373805
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical tuning knobs and process parameters in terms of a given figure-of-merit for a Device Under Test (DUT). This is often manually conducted by experienced experts. However, with increasingly complex chips, manual inspection on a large amount of raw variables has become more challenging. In this work, we leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.

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