End-to-end codesign of Hessian-aware quantized neural networks for FPGAs
and ASICs
- URL: http://arxiv.org/abs/2304.06745v1
- Date: Thu, 13 Apr 2023 18:00:01 GMT
- Title: End-to-end codesign of Hessian-aware quantized neural networks for FPGAs
and ASICs
- Authors: Javier Campos, Zhen Dong, Javier Duarte, Amir Gholami, Michael W.
Mahoney, Jovan Mitrevski, Nhan Tran
- Abstract summary: We develop an end-to-end workflow for the training and implementation of co-designed neural networks (NNs)
This makes efficient NN implementations in hardware accessible to nonexperts, in a single open-sourced workflow.
We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40 MHz collision rate of the Large Hadron Collider (LHC)
We implement an optimized mixed-precision NN for high-momentum particle jets in simulated LHC proton-proton collisions.
- Score: 49.358119307844035
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: We develop an end-to-end workflow for the training and implementation of
co-designed neural networks (NNs) for efficient field-programmable gate array
(FPGA) and application-specific integrated circuit (ASIC) hardware. Our
approach leverages Hessian-aware quantization (HAWQ) of NNs, the Quantized Open
Neural Network Exchange (QONNX) intermediate representation, and the hls4ml
tool flow for transpiling NNs into FPGA and ASIC firmware. This makes efficient
NN implementations in hardware accessible to nonexperts, in a single
open-sourced workflow that can be deployed for real-time machine learning
applications in a wide range of scientific and industrial settings. We
demonstrate the workflow in a particle physics application involving trigger
decisions that must operate at the 40 MHz collision rate of the CERN Large
Hadron Collider (LHC). Given the high collision rate, all data processing must
be implemented on custom ASIC and FPGA hardware within a strict area and
latency. Based on these constraints, we implement an optimized mixed-precision
NN classifier for high-momentum particle jets in simulated LHC proton-proton
collisions.
Related papers
- Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition [0.0]
Machine learning can be implemented in detector electronics for intelligent data processing and acquisition.
implementation of ML in real-time at colliders requires very low latencies that are unachievable with a software-based approach.
An analysis of neural network inference efficiency is presented, focusing on the application of collider trigger algorithms in field programmable gate arrays.
arXiv Detail & Related papers (2024-11-18T15:59:30Z) - Ultra-low latency quantum-inspired machine learning predictors implemented on FPGA [0.0]
Tree Networks (TNs) are a computational paradigm used for representing quantum many-body systems.
Recent works have shown how TNs can also be applied to perform Machine Learning (ML) tasks.
We study the use of TTNs in high-frequency real-time applications by exploiting the low- hardware of the Field-Programmable Gate Array (FPGA) technology.
arXiv Detail & Related papers (2024-09-24T13:21:21Z) - Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA [20.629635991749808]
This paper proposes an algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs.
At the algorithm level, we propose novel multi-exit dropout-based BayesNNs with reduced computational and memory overheads.
At the hardware level, this paper introduces a transformation framework that can generate FPGA-based accelerators for the proposed efficient BayesNNs.
arXiv Detail & Related papers (2024-06-20T17:08:42Z) - Reconfigurable Distributed FPGA Cluster Design for Deep Learning
Accelerators [59.11160990637615]
We propose a distributed system based on lowpower embedded FPGAs designed for edge computing applications.
The proposed system can simultaneously execute diverse Neural Network (NN) models, arrange the graph in a pipeline structure, and manually allocate greater resources to the most computationally intensive layers of the NN graph.
arXiv Detail & Related papers (2023-05-24T16:08:55Z) - Intelligence Processing Units Accelerate Neuromorphic Learning [52.952192990802345]
Spiking neural networks (SNNs) have achieved orders of magnitude improvement in terms of energy consumption and latency.
We present an IPU-optimized release of our custom SNN Python package, snnTorch.
arXiv Detail & Related papers (2022-11-19T15:44:08Z) - Decomposition of Matrix Product States into Shallow Quantum Circuits [62.5210028594015]
tensor network (TN) algorithms can be mapped to parametrized quantum circuits (PQCs)
We propose a new protocol for approximating TN states using realistic quantum circuits.
Our results reveal one particular protocol, involving sequential growth and optimization of the quantum circuit, to outperform all other methods.
arXiv Detail & Related papers (2022-09-01T17:08:41Z) - FPGA-optimized Hardware acceleration for Spiking Neural Networks [69.49429223251178]
This work presents the development of a hardware accelerator for an SNN, with off-line training, applied to an image recognition task.
The design targets a Xilinx Artix-7 FPGA, using in total around the 40% of the available hardware resources.
It reduces the classification time by three orders of magnitude, with a small 4.5% impact on the accuracy, if compared to its software, full precision counterpart.
arXiv Detail & Related papers (2022-01-18T13:59:22Z) - Graph Neural Networks for Charged Particle Tracking on FPGAs [2.6402980149746913]
The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem.
Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task.
We introduce an automated translation workflow, integrated into a broader tool called $textthls4ml$, for converting GNNs into firmware for field-programmable gate arrays (FPGAs)
arXiv Detail & Related papers (2021-12-03T17:56:10Z) - Quantized Neural Networks via {-1, +1} Encoding Decomposition and
Acceleration [83.84684675841167]
We propose a novel encoding scheme using -1, +1 to decompose quantized neural networks (QNNs) into multi-branch binary networks.
We validate the effectiveness of our method on large-scale image classification, object detection, and semantic segmentation tasks.
arXiv Detail & Related papers (2021-06-18T03:11:15Z) - A Learning Framework for n-bit Quantized Neural Networks toward FPGAs [20.83904734716565]
This paper proposes a novel learning framework for n-bit QNNs, whose weights are constrained to the power of two.
We also propose a novel QNN structure named n-BQ-NN, which uses shift operation to replace the multiply operation.
Experiments show that our n-BQ-NN with our SVPE can execute 2.9 times faster than with the vector processing element (VPE) in inference.
arXiv Detail & Related papers (2020-04-06T04:21:24Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.