Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition

• URL: http://arxiv.org/abs/2306.05021v2
• Date: Thu, 22 Jun 2023 15:44:01 GMT
• Title: Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition
• Authors: Zhewen Yu, Christos-Savvas Bouganis
• Abstract summary: We propose a framework for mapping CNNs onto FPGAs based on a novel tensor decomposition method called Mixed-TD. The proposed method applies layer-specific Singular Value Decomposition (SVD) and Canonical Polyadic Decomposition (CPD) in a mixed manner, achieving 1.73x to 10.29x throughput per DSP to state-of-the-art CNNs.
• Score: 7.221206118679026
• License: http://creativecommons.org/licenses/by-sa/4.0/
• Abstract: Neural Network designs are quite diverse, from VGG-style to ResNet-style, and from Convolutional Neural Networks to Transformers. Towards the design of efficient accelerators, many works have adopted a dataflow-based, inter-layer pipelined architecture, with a customised hardware towards each layer, achieving ultra high throughput and low latency. The deployment of neural networks to such dataflow architecture accelerators is usually hindered by the available on-chip memory as it is desirable to preload the weights of neural networks on-chip to maximise the system performance. To address this, networks are usually compressed before the deployment through methods such as pruning, quantization and tensor decomposition. In this paper, a framework for mapping CNNs onto FPGAs based on a novel tensor decomposition method called Mixed-TD is proposed. The proposed method applies layer-specific Singular Value Decomposition (SVD) and Canonical Polyadic Decomposition (CPD) in a mixed manner, achieving 1.73x to 10.29x throughput per DSP to state-of-the-art CNNs. Our work is open-sourced: https://github.com/Yu-Zhewen/Mixed-TD

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