Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs

• URL: http://arxiv.org/abs/2401.08696v1
• Date: Sun, 14 Jan 2024 07:24:08 GMT
• Title: Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
• Authors: Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo
• Abstract summary: We propose a hierarchical post-route QoR prediction approach for FPGA HLS. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes.
• Score: 25.920672727699984
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route quality of results (QoR) are considered during optimization. To tackle this issue, we propose a hierarchical post-route QoR prediction approach for FPGA HLS, which features: (1) a modeling flow that directly estimates latency and post-route resource usage from C/C++ programs; (2) a graph construction method that effectively represents the control and data flow graph of source code and effects of HLS pragmas; and (3) a hierarchical GNN training and prediction method capable of capturing the impact of loop hierarchies. Experimental results show that our method presents a prediction error of less than 10% for different types of QoR metrics, which gains tremendous improvement compared with the state-of-the-art GNN methods. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91% on average.

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