A 3D Memristor Architecture for In-Memory Computing Demonstrated with SHA3

• URL: http://arxiv.org/abs/2402.09545v1
• Date: Wed, 14 Feb 2024 19:43:18 GMT
• Title: A 3D Memristor Architecture for In-Memory Computing Demonstrated with SHA3
• Abstract summary: Security is a growing problem that needs hardware support. Memristors provide an alternative technology for hardware-supported security implementation. This paper presents a specific technique that utilizes the benefits of hybrid CMOS-memristors technology demonstrated with SHA3 over implementations that use only memristor technology.
• Score: 1.024113475677323
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Security is a growing problem that needs hardware support. Memristors provide an alternative technology for hardware-supported security implementation. This paper presents a specific technique that utilizes the benefits of hybrid CMOS-memristors technology demonstrated with SHA3 over implementations that use only memristor technology. In the proposed technique, SHA3 is implemented in a set of perpendicular crossbar arrays structured to facilitate logic implementation and circular bit rotation (Rho operation), which is perhaps the most complex operation in SHA3 when carried out in memristor arrays. The Rho operation itself is implemented with CMOS multiplexers (MUXs). The proposed accelerator is standby power-free and circumvents the memory access bottleneck in conventional computers. In addition, our design obscures the intermediate values from the I/O interface and outperforms the state-of-the-art memristor-based designs in terms of size and energy. Demonstrating the memristor implementation of SHA3 provides an impetus for utilizing memristors in information security applications.

Related papers

• SAM3-I: Segment Anything with Instructions [86.92593395772029]
  We present SAM3-I, an enhanced framework that unifies concept-level understanding and instructionlevel reasoning within the SAM family.<n>We design a structured instruction taxonomy spanning concept, simple, and complex levels, and develop a scalable data engine to construct a dataset with diverse instruction-mask pairs.
  arXiv  Detail & Related papers  (2025-12-04T09:00:25Z)
• CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing [2.1893572076171526]
  CryptoSRAM is a cryptographic architecture that performs operations directly within the MCU's standard array.<n>By repurposing the memory array into a massively parallel processing fabric, CryptoSRAM eliminates the data movement bottleneck.<n>For common cryptographic kernels, CryptoSRAM achieves throughput improvements of up to 74$times$ and 67$times$ for AES and SHA3, respectively.
  arXiv  Detail & Related papers  (2025-09-26T22:36:45Z)
• Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V [0.0]
  Hardware-assisted cryptographic instructions, such as Intel's AES-NI and ARM's custom instructions for encryption workloads, have demonstrated substantial performance improvements.<n>However, efficient SHA-3 acceleration remains an open problem due to its distinct permutation-based structure and memory access patterns.<n>This study investigates the architectural challenges of embedding a SHA-3 permutation operation as a custom instruction within a general-purpose processor.
  arXiv  Detail & Related papers  (2025-08-28T10:57:13Z)
• gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography [15.39096542261856]
  Elliptic Curve Cryptography (ECC) is an encryption method that provides security comparable to traditional techniques like Rivest-Shamir-Adleman (RSA) ECC is still hindered by the significant performance overhead associated with elliptic curve (EC) operations. This paper presents gECC, a versatile framework for ECC optimized for GPU architectures.
  arXiv  Detail & Related papers  (2024-12-22T01:50:50Z)
• Nemesis: Noise-randomized Encryption with Modular Efficiency and Secure Integration in Machine Learning Systems [1.3824176915623292]
  Nemesis is a framework that accelerates FHE-based machine learning systems without compromising accuracy or security. We prove the security of Nemesis under standard cryptographic assumptions. Results show that Nemesis significantly reduces the computational overhead of FHE-based ML systems.
  arXiv  Detail & Related papers  (2024-12-18T22:52:12Z)
• ThunderKittens: Simple, Fast, and Adorable AI Kernels [43.32681787348603]
  We present ThunderKittens (TK), a framework for writing performant AI kernels while remaining easy to use and maintain. We show the value of TK by providing kernels that match or outperform prior kernels for a range of AI operations.
  arXiv  Detail & Related papers  (2024-10-27T10:07:16Z)
• Efficient and accurate neural field reconstruction using resistive memory [52.68088466453264]
  Traditional signal reconstruction methods on digital computers face both software and hardware challenges. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications.
  arXiv  Detail & Related papers  (2024-04-15T09:33:09Z)
• ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM [7.949839381468341]
  Elliptic curve cryptography (ECC) is widely used in security applications such as public key cryptography (CPK) and zero-knowledge proofs (ZKP)
  arXiv  Detail & Related papers  (2024-02-21T22:26:44Z)
• Experimental demonstration of magnetic tunnel junction-based computational random-access memory [4.640906373267124]
  "Computational random-access memory (CRAM) has emerged to address this fundamental limitation" CRAM performs logic operations directly using the memory cells themselves, without having the data ever leave the memory. Technology could have a significant impact on power- and energy-demanding applications of machine intelligence.
  arXiv  Detail & Related papers  (2023-12-21T19:28:54Z)
• MCUFormer: Deploying Vision Transformers on Microcontrollers with Limited Memory [76.02294791513552]
  We propose a hardware-algorithm co-optimizations method called MCUFormer to deploy vision transformers on microcontrollers with extremely limited memory. Experimental results demonstrate that our MCUFormer achieves 73.62% top-1 accuracy on ImageNet for image classification with 320KB memory.
  arXiv  Detail & Related papers  (2023-10-25T18:00:26Z)
• Code Polymorphism Meets Code Encryption: Confidentiality and Side-Channel Protection of Software Components [0.0]
  PolEn is a toolchain and a processor architecturethat combine countermeasures in order to provide an effective mitigation of side-channel attacks. Code encryption is supported by a processor extension such that machineinstructions are only decrypted inside the CPU. Code polymorphism is implemented by software means. It regularly changes the observablebehaviour of the program, making it unpredictable for an attacker.
  arXiv  Detail & Related papers  (2023-10-11T09:16:10Z)
• SOCI^+: An Enhanced Toolkit for Secure OutsourcedComputation on Integers [50.608828039206365]
  We propose SOCI+ which significantly improves the performance of SOCI. SOCI+ employs a novel (2, 2)-threshold Paillier cryptosystem with fast encryption and decryption as its cryptographic primitive. Compared with SOCI, our experimental evaluation shows that SOCI+ is up to 5.4 times more efficient in computation and 40% less in communication overhead.
  arXiv  Detail & Related papers  (2023-09-27T05:19:32Z)
• Multiplierless Design of High-Speed Very Large Constant Multiplications [3.5382618288815495]
  In cryptographic algorithms, the constants to be multiplied by a variable can be very large due to security requirements. We introduce an electronic design automation tool, called LEIGER, which can automatically generate the realizations of very large constant multiplications.
  arXiv  Detail & Related papers  (2023-09-11T15:35:02Z)
• FusionAI: Decentralized Training and Deploying LLMs with Massive Consumer-Level GPUs [57.12856172329322]
  We envision a decentralized system unlocking the potential vast untapped consumer-level GPU. This system faces critical challenges, including limited CPU and GPU memory, low network bandwidth, the variability of peer and device heterogeneity.
  arXiv  Detail & Related papers  (2023-09-03T13:27:56Z)
• A Memristive Based Design of a Core Digital Circuit for Elliptic Curve Cryptography [0.5266869303483376]
  Memristor devices and CMOS transistors are working together to form a hybrid CMOS-memristor circuit for XAX- Module. The proposed design was implemented using Pt /TaOx/Ta memristor device and simulated in Cadence Virtuoso.
  arXiv  Detail & Related papers  (2022-03-27T17:50:41Z)
• Brain-inspired Cognition in Next Generation Racetrack Memories [0.6850683267295249]
  Hyperdimensional computing (HDC) is an emerging computational framework inspired by the brain that operates on vectors with thousands of dimensions to emulate cognition. This paper presents an architecture based on racetrack memory (RTM) to conduct and accelerate the entire HDC framework within the memory. The proposed solution requires minimal additional CMOS circuitry and uses a read operation across multiple domains in RTMs called transverse read (TR) to realize exclusive-or (XOR) and addition operations.
  arXiv  Detail & Related papers  (2021-11-03T14:21:39Z)
• Safe RAN control: A Symbolic Reinforcement Learning Approach [62.997667081978825]
  We present a Symbolic Reinforcement Learning (SRL) based architecture for safety control of Radio Access Network (RAN) applications. We provide a purely automated procedure in which a user can specify high-level logical safety specifications for a given cellular network topology. We introduce a user interface (UI) developed to help a user set intent specifications to the system, and inspect the difference in agent proposed actions.
  arXiv  Detail & Related papers  (2021-06-03T16:45:40Z)
• CARAFE++: Unified Content-Aware ReAssembly of FEatures [132.49582482421246]
  We propose unified Content-Aware ReAssembly of FEatures (CARAFE++), a universal, lightweight and highly effective operator to fulfill this goal. CARAFE++ generates adaptive kernels on-the-fly to enable instance-specific content-aware handling. It shows consistent and substantial gains across all the tasks with negligible computational overhead.
  arXiv  Detail & Related papers  (2020-12-07T07:34:57Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.