Hardware-Assisted Parameterized Circuit Execution

• URL: http://arxiv.org/abs/2409.03725v1
• Date: Thu, 5 Sep 2024 17:30:36 GMT
• Title: Hardware-Assisted Parameterized Circuit Execution
• Authors: Abhi D. Rajagopala, Akel Hashim, Neelay Fruitwala, Gang Huang, Yilun Xu, Jordan Hines, Irfan Siddiqi, Katherine Klymko, Kasra Nowrouzi,
• Abstract summary: We develop a hardware-assisted protocol for executing parameterized circuits on our FPGA-based control hardware, QubiC. This work demonstrates significant speed ups in the total execution time for several different classes of quantum circuits.
• Score: 7.804530685405802
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Standard compilers for quantum circuits decompose arbitrary single-qubit gates into a sequence of physical X(pi/2) pulses and virtual-Z phase gates. Consequently, many circuit classes implement different logic operations but have an equivalent structure of physical pulses that only differ by changes in virtual phases. When many structurally-equivalent circuits need to be measured, generating sequences for each circuit is unnecessary and cumbersome, since compiling and loading sequences onto classical control hardware is a primary bottleneck in quantum circuit execution. In this work, we develop a hardware-assisted protocol for executing parameterized circuits on our FPGA-based control hardware, QubiC. This protocol relies on a hardware-software co-design technique in which software identifies structural equivalency in circuits and "peels" off the relevant parameterized angles to reduce the overall waveform compilation time. The hardware architecture then performs real-time "stitching" of the parameters in the circuit to measure circuits that implement a different overall logical operation. This work demonstrates significant speed ups in the total execution time for several different classes of quantum circuits.

Related papers

• Breaking Down Quantum Compilation: Profiling and Identifying Costly Passes [40.11095094521714]
  We perform a preliminary analysis of the quantum circuit compilation process in Qiskit. We identify the tasks that most strongly impact the overall compilation time. Our results indicate that, as the desired level of optimization increases, circuit synthesis and gate passes become the dominant tasks.
  arXiv  Detail & Related papers  (2025-04-21T14:45:01Z)
• Runtime Reduction in Linear Quantum Charge-Coupled Devices using the Parity Flow Formalism [0.32985979395737786]
  We show that physical SWAP gates can be eliminated in linear hardware architectures without increasing the total number of two-qubit operations. This has a significant impact on the execution time of quantum circuits in linear Quantum Charge-Coupled Devices.
  arXiv  Detail & Related papers  (2024-10-21T18:00:29Z)
• Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
  We develop a reinforcement learning-based quantum compiler for a superconducting processor. We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths. Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
  arXiv  Detail & Related papers  (2024-06-18T01:49:48Z)
• CktGNN: Circuit Graph Neural Network for Electronic Design Automation [67.29634073660239]
  This paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing. We introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains $10$K distinct operational amplifiers. Our work paves the way toward a learning-based open-sourced design automation for analog circuits.
  arXiv  Detail & Related papers  (2023-08-31T02:20:25Z)
• One-Time Compilation of Device-Level Instructions for Quantum Subroutines [21.79238078751215]
  We develop a device-level partial-compilation (DLPC) technique that reduces compilation overhead to nearly constant. We execute this modified pipeline on real trapped-ion quantum computers and observe significant reductions in compilation time.
  arXiv  Detail & Related papers  (2023-08-21T15:23:09Z)
• Majorization-based benchmark of the complexity of quantum processors [105.54048699217668]
  We numerically simulate and characterize the operation of various quantum processors. We identify and assess quantum complexity by comparing the performance of each device against benchmark lines. We find that the majorization-based benchmark holds as long as the circuits' output states have, on average, high purity.
  arXiv  Detail & Related papers  (2023-04-10T23:01:10Z)
• Universal qudit gate synthesis for transmons [44.22241766275732]
  We design a superconducting qudit-based quantum processor. We propose a universal gate set featuring a two-qudit cross-resonance entangling gate. We numerically demonstrate the synthesis of $rm SU(16)$ gates for noisy quantum hardware.
  arXiv  Detail & Related papers  (2022-12-08T18:59:53Z)
• Quantum circuit debugging and sensitivity analysis via local inversions [62.997667081978825]
  We present a technique that pinpoints the sections of a quantum circuit that affect the circuit output the most. We demonstrate the practicality and efficacy of the proposed technique by applying it to example algorithmic circuits implemented on IBM quantum machines.
  arXiv  Detail & Related papers  (2022-04-12T19:39:31Z)
• Fast Swapping in a Quantum Multiplier Modelled as a Queuing Network [64.1951227380212]
  We propose that quantum circuits can be modeled as queuing networks. Our method is scalable and has the potential speed and precision necessary for large scale quantum circuit compilation.
  arXiv  Detail & Related papers  (2021-06-26T10:55:52Z)
• Deterministic Algorithms for Compiling Quantum Circuits with Recurrent Patterns [0.0]
  Current quantum processors are noisy, have limited coherence and imperfect gate implementations. We present novel deterministic algorithms for compiling recurrent quantum circuit patterns in time. Our solution produces unmatched results on RyRz circuits.
  arXiv  Detail & Related papers  (2021-02-17T13:59:12Z)
• Enabling Multi-programming Mechanism for Quantum Computing in the NISQ Era [0.0]
  NISQ devices have several physical limitations and unavoidable noisy quantum operations. Only small circuits can be executed on a quantum machine to get reliable results. We propose a Quantum Multi-programming Compiler (QuMC) to execute multiple quantum circuits on quantum hardware simultaneously.
  arXiv  Detail & Related papers  (2021-02-10T08:46:16Z)
• Verifying Results of the IBM Qiskit Quantum Circuit Compilation Flow [7.619626059034881]
  We propose an efficient scheme for quantum circuit equivalence checking. The proposed scheme allows to verify even large circuit instances with tens of thousands of operations within seconds or even less.
  arXiv  Detail & Related papers  (2020-09-04T19:58:53Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.