Machine Learning Enhanced Quantum State Tomography on FPGA
- URL: http://arxiv.org/abs/2501.04327v1
- Date: Wed, 08 Jan 2025 07:59:40 GMT
- Title: Machine Learning Enhanced Quantum State Tomography on FPGA
- Authors: Hsun-Chung Wu, Hsien-Yi Hsieh, Zhi-Kai Xu, Hua Li Chen, Zi-Hao Shi, Po-Han Wang, Popo Yang, Ole Steuernagel, Chien-Ming Wu, Ray-Kuang Lee,
- Abstract summary: Machine learning techniques have opened new avenues for real-time quantum state tomography (QST)
We demonstrate the deployment of machine learning-based QST onto edge devices, specifically utilizing field programmable gate arrays (FPGAs)
- Score: 0.12171407135748794
- License:
- Abstract: Machine learning techniques have opened new avenues for real-time quantum state tomography (QST). In this work, we demonstrate the deployment of machine learning-based QST onto edge devices, specifically utilizing field programmable gate arrays (FPGAs). This implementation is realized using the {\it Vitis AI Integrated Development Environment} provided by AMD\textsuperscript \textregistered~Inc. Compared to the Graphics Processing Unit (GPU)-based machine learning QST, our FPGA-based one reduces the average inference time by an order of magnitude, from 38 ms to 2.94 ms, but only sacrifices the average fidelity about $1\% $ reduction (from 0.99 to 0.98). The FPGA-based QST offers a highly efficient and precise tool for diagnosing quantum states, marking a significant advancement in the practical applications for quantum information processing and quantum sensing.
Related papers
- SeQUeNCe GUI: An Extensible User Interface for Discrete Event Quantum Network Simulations [55.2480439325792]
SeQUeNCe is an open source simulator of quantum network communication.
We implement a graphical user interface which maintains the core principles of SeQUeNCe.
arXiv Detail & Related papers (2025-01-15T19:36:09Z) - AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs [0.6553587309274792]
AMARETTO is designed for quantum computing emulation on low-tier Field-Programmable gate arrays (FPGAs)
It simplifies and accelerates the verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates.
arXiv Detail & Related papers (2024-11-14T10:01:53Z) - Technology and Performance Benchmarks of IQM's 20-Qubit Quantum Computer [56.435136806763055]
IQM Quantum Computers is described covering both the QPU and the rest of the full-stack quantum computer.
The focus is on a 20-qubit quantum computer featuring the Garnet QPU and its architecture, which we will scale up to 150 qubits.
We present QPU and system-level benchmarks, including a median 2-qubit gate fidelity of 99.5% and genuinely entangling all 20 qubits in a Greenberger-Horne-Zeilinger (GHZ) state.
arXiv Detail & Related papers (2024-08-22T14:26:10Z) - Demonstrating the Potential of Adaptive LMS Filtering on FPGA-Based Qubit Control Platforms for Improved Qubit Readout in 2D and 3D Quantum Processing Units [3.348076908667385]
This abstract presents our research intended for optimizing readout pulse fidelity for 2D and 3D Quantum Processing Units (QPUs)
We focus on the application of the Least Mean Squares (LMS) adaptive filtering algorithm to enhance the accuracy and efficiency of qubit state detection.
Our preliminary results demonstrate the LMS filter's capability to maintain high readout accuracy while efficiently managing FPGA resources.
arXiv Detail & Related papers (2024-08-01T20:42:49Z) - Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
We develop a reinforcement learning-based quantum compiler for a superconducting processor.
We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths.
Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
arXiv Detail & Related papers (2024-06-18T01:49:48Z) - Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout [0.7367855181841242]
Field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC)
An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes.
A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA.
arXiv Detail & Related papers (2024-04-26T20:59:23Z) - Compilation of algorithm-specific graph states for quantum circuits [55.90903601048249]
We present a quantum circuit compiler that prepares an algorithm-specific graph state from quantum circuits described in high level languages.
The computation can then be implemented using a series of non-Pauli measurements on this graph state.
arXiv Detail & Related papers (2022-09-15T14:52:31Z) - QSAN: A Near-term Achievable Quantum Self-Attention Network [73.15524926159702]
Self-Attention Mechanism (SAM) is good at capturing the internal connections of features.
A novel Quantum Self-Attention Network (QSAN) is proposed for image classification tasks on near-term quantum devices.
arXiv Detail & Related papers (2022-07-14T12:22:51Z) - Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark [11.575901540758574]
We present our development experience for the Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms.
We use the open-source hls4ml and FINN perJ, which aim to democratize AI- hardware codesign of optimized neural networks on FPGAs.
The solutions are deployed on system-on-chip (Pynq-Z2) and pure FPGA (Arty A7-100T) platforms.
arXiv Detail & Related papers (2022-06-23T15:57:17Z) - VAQF: Fully Automatic Software-hardware Co-design Framework for Low-bit
Vision Transformer [121.85581713299918]
We propose VAQF, a framework that builds inference accelerators on FPGA platforms for quantized Vision Transformers (ViTs)
Given the model structure and the desired frame rate, VAQF will automatically output the required quantization precision for activations.
This is the first time quantization has been incorporated into ViT acceleration on FPGAs.
arXiv Detail & Related papers (2022-01-17T20:27:52Z) - Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle
Reconstruction in High Energy Physics [11.125632758828266]
We discuss how to design distance-weighted graph networks that can be executed with a latency of less than 1$mumathrms$ on an FPGA.
We consider a representative task associated to particle reconstruction and identification in a next-generation calorimeter operating at a particle collider.
We convert the compressed models into firmware to be implemented on an FPGA.
arXiv Detail & Related papers (2020-08-08T21:26:31Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.