Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction

• URL: http://arxiv.org/abs/2501.12470v1
• Date: Tue, 21 Jan 2025 19:39:03 GMT
• Title: Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction
• Authors: Bao Bach, Ilya Safro, Ed Younis,
• Abstract summary: This work presents a novel unifying abstraction, called the position graph, for different types of hardware architectures. We model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures and enable high-quality, superconducting scalable compilation methods. This approach generates native, executable circuits and ion instructions on the hardware that adheres to the physical constraints of shuttling-based quantum computers.
• Score: 0.9199465050084297
• License:
• Abstract: With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial factor in deciding the success of the implementation. There has been rich research and development in compilation techniques for the superconducting-qubit regime. In contrast, the trapped-ion architectures, currently leading in robust quantum computations due to their reliable operations, do not have many competitive compilation strategies. This work presents a novel unifying abstraction, called the position graph, for different types of hardware architectures. Using this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures and enable high-quality, scalable superconducting compilation methods. In particular, we devise a scheduling algorithm called SHuttling-Aware PERmutative heuristic search algorithm (SHAPER) to tackle the complex constraints and dynamics of trapped-ion QCCD with the cooperation of state-of-the-art permutation-aware mapping. This approach generates native, executable circuits and ion instructions on the hardware that adheres to the physical constraints of shuttling-based quantum computers. Using the position graph abstraction, we evaluate our algorithm on theorized and actual architectures. Our algorithm can successfully compile programs for these architectures where other state-of-the-art algorithms fail. In the cases when other algorithms complete, our algorithm produces a schedule that is $14\%$ faster on average, up to $69\%$ in the best case.\\ {\bf Reproducibility:} source code and computational results are available at $[$will be added upon acceptance$]$

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