Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits

• URL: http://arxiv.org/abs/2502.08949v1
• Date: Thu, 13 Feb 2025 04:15:20 GMT
• Title: Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits
• Authors: Sungyoung Lee, Ziyi Wang, Seunggeun Kim, Taekyun Lee, David Z. Pan,
• Abstract summary: We introduce DICE: Device-level Integrated Circuits, the first self-supervised pretrained graph neural network (GNN) model for any circuit expressed at the device level. DICE achieves substantial performance gains across three downstream tasks, underscoring its effectiveness for both analog and digital circuits.
• Score: 8.117059763475488
• License:
• Abstract: Self-supervised graph representation learning has driven significant advancements in domains such as social network analysis, molecular design, and electronics design automation (EDA). However, prior works in EDA have mainly focused on the representation of gate-level digital circuits, failing to capture analog and mixed-signal circuits. To address this gap, we introduce DICE: Device-level Integrated Circuits Encoder, the first self-supervised pretrained graph neural network (GNN) model for any circuit expressed at the device level. DICE is a message-passing neural network (MPNN) trained through graph contrastive learning, and its pretraining process is simulation-free, incorporating two novel data augmentation techniques. Experimental results demonstrate that DICE achieves substantial performance gains across three downstream tasks, underscoring its effectiveness for both analog and digital circuits.

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