A Novel Interactive-Guided Differential Testing Approach for FPGA Simulation Debugger Tools
- URL: http://arxiv.org/abs/2503.01138v1
- Date: Mon, 03 Mar 2025 03:38:20 GMT
- Title: A Novel Interactive-Guided Differential Testing Approach for FPGA Simulation Debugger Tools
- Authors: Shikai Guo, Xiaoyu Wang, Xiaochen Li, Zhihao Xu, He Jiang,
- Abstract summary: We propose a interactive differential testing approach called DB-Hunter to detect bugs in Vivado's FPGA chip debugger tools.<n>DB-Hunter consists of three components: RTL design transformation component, debug action transformation component, and interactive differential testing component.<n>In three months, DB-Hunter reported 18 issues, including 10 confirmed as bugs by Xilinx Support, 6 bugs had been fixed in last version.
- Score: 9.441160923314227
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: Field-Programmable Gate Array (FPGA) development tool chains are widely used in FPGA design, simulation, and verification in critical areas like communications, automotive electronics, and aerospace. Commercial FPGA tool chains such as Xilinx' Vivado aids developers in swiftly identifying and rectifying bugs and issues in FPGA designs through a robust built-in debugger, ensuring the correctness and development efficiency of the FPGA design. Hardening such FPGA chip debugger tools by testing is crucial since engineers might misinterpret code and introduce incorrect fixes, leading to security risks. However, FPGA chip debugger tools are challenging to test as they require assessing both RTL designs and a series of debugging actions, including setting breakpoints and stepping through the code. To address this issue, we propose a interactive differential testing approach called DB-Hunter to detect bugs in Vivado's FPGA chip debugger tools. Specifically, DB-Hunter consists of three components: RTL design transformation component, debug action transformation component, and interactive differential testing component. By performing RTL design and debug action transformations, DB-Hunter generates diverse and complex RTL designs and debug actions, to thoroughly test the Vivado debugger using interactive differential testing to detect bugs. In three months, DB-Hunter reported 18 issues, including 10 confirmed as bugs by Xilinx Support, 6 bugs had been fixed in last version.
Related papers
- LocalV: Exploiting Information Locality for IP-level Verilog Generation [45.78831906080782]
The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design.<n>Existing approaches-including fine-tuned domain-specific models and advanced agent-based systems-struggle to scale to industrial IP-level design tasks.<n>We propose LocalV, a multi-agent framework that leverages information locality in modular hardware design.
arXiv Detail & Related papers (2026-01-31T13:01:16Z) - LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns [9.542805275381566]
Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrated at the system level.<n>We introduce LAUDE, a unified unit-test generation and debug framework for hardware designs that cross-pollinates the semantic understanding of the design source code with the Chain-of-Thought (CoT) reasoning capabilities of foundational Large-Language Models (LLMs)<n>We apply LAUDE with closed- and open-source LLMs to a large corpus of buggy hardware design codes derived from the VerilogEval dataset, where generated unit tests detected bugs in
arXiv Detail & Related papers (2026-01-06T04:00:07Z) - InspectCoder: Dynamic Analysis-Enabled Self Repair through interactive LLM-Debugger Collaboration [71.18377595277018]
Large Language Models (LLMs) frequently generate buggy code with complex logic errors that are challenging to diagnose.<n>We present InspectCoder, the first agentic program repair system that empowers LLMs to actively conduct dynamic analysis via interactive debugger control.
arXiv Detail & Related papers (2025-10-21T06:26:29Z) - FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures [8.530369312832084]
We present FV Debug, an intelligent system that transforms failure traces into actionable insights.<n>Our approach features a novel pipeline: (1) Causal Graph Synthesis that structures failure traces into directed acyclic graphs, (2) Graph Scanner using batched Large Language Model (LLM) analysis with for-and-against prompting to identify suspicious nodes, and (3) Insight Rover leveraging agentic narrative exploration to generate high-level causal explanations.
arXiv Detail & Related papers (2025-09-16T20:22:10Z) - Compiler Bugs Detection in Logic Synthesis Tools via Linear Upper Confidence Bound [11.123007674634936]
Lin-Hunter is a novel testing framework designed to enhance the diversity of HDL test cases and the efficiency of FPGA logic synthesis tool validation.<n>Our method has discovered 18 unique bugs, including 10 previously unreported defects, which have been confirmed by official developers.
arXiv Detail & Related papers (2025-09-01T05:54:48Z) - Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers [8.895692098710716]
We propose a guided mutation strategy based on Bayesian optimization called LSC-Fuzz to detect bugs in FPGA logic synthesis compilers.<n>Through three months, LSC-Fuzz has found 16 bugs, 12 of these has been confirmed by official technical support.
arXiv Detail & Related papers (2025-08-25T06:41:36Z) - A Novel Mutation Based Method for Detecting FPGA Logic Synthesis Tool Bugs [7.8865444084780965]
We propose VERMEI, a new method for testing FPGA logic synthesis tools.<n> VERMEI consists of three modules: preprocessing, equivalent mutation, and bug identification.<n>Within five months, VERMEI reported 15 bugs to vendors, 9 of which were confirmed as new.
arXiv Detail & Related papers (2025-08-21T13:11:59Z) - Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules [49.1574468325115]
Hardware Trojans (HTs) enable attackers to execute unauthorized software or gain illicit access to privileged operations.<n>This manuscript introduces a hardware-based methodology for detecting runtime HT activations using Error Correction Codes (ECCs) on a RISC-V microprocessor.
arXiv Detail & Related papers (2025-06-18T12:37:14Z) - Detecting the Root Cause Code Lines in Bug-Fixing Commits by Heterogeneous Graph Learning [1.5213722322518697]
Automated defect prediction tools can proactively identify software changes prone to defects within software projects.<n>Existing work in heterogeneous and complex software projects continues to face challenges, such as struggling with heterogeneous commit structures and ignoring cross-line dependencies in code changes.<n>We propose an approach called RC_Detector, which consists of three main components: the bug-fixing graph construction component, the code semantic aggregation component, and the cross-line semantic retention component.
arXiv Detail & Related papers (2025-05-02T05:39:50Z) - ToolCoder: A Systematic Code-Empowered Tool Learning Framework for Large Language Models [49.04652315815501]
Tool learning has emerged as a crucial capability for large language models (LLMs) to solve complex real-world tasks through interaction with external tools.
We propose ToolCoder, a novel framework that reformulates tool learning as a code generation task.
arXiv Detail & Related papers (2025-02-17T03:42:28Z) - A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs [7.519011820592022]
It is challenging to jointly develop and debug host software and FPGA hardware.<n>Changes to the hardware design require a time-consuming FPGA synthesis process.<n>A VM-HDL co-simulation framework is designed to run the same software, operating system, and hardware designs as the target physical system.
arXiv Detail & Related papers (2025-01-19T22:06:36Z) - From Code to Correctness: Closing the Last Mile of Code Generation with Hierarchical Debugging [5.910272203315325]
We introduce Multi-Granularity Debugger (MG Debugger), a hierarchical code debugger by isolating, identifying, and resolving bugs at various levels of granularity.
MG Debugger decomposes problematic code into a hierarchical tree structure of subfunctions, with each level representing a particular granularity of error.
It achieves an 18.9% improvement in accuracy over seed generations in HumanEval and a 97.6% repair success rate in HumanEvalFix.
arXiv Detail & Related papers (2024-10-02T03:57:21Z) - Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA [20.629635991749808]
This paper proposes an algorithm and hardware co-design framework that can generate field-programmable gate array (FPGA)-based accelerators for efficient BayesNNs.
At the algorithm level, we propose novel multi-exit dropout-based BayesNNs with reduced computational and memory overheads.
At the hardware level, this paper introduces a transformation framework that can generate FPGA-based accelerators for the proposed efficient BayesNNs.
arXiv Detail & Related papers (2024-06-20T17:08:42Z) - VDebugger: Harnessing Execution Feedback for Debugging Visual Programs [103.61860743476933]
We introduce V Debugger, a critic-refiner framework trained to localize and debug visual programs by tracking execution step by step.
V Debugger identifies and corrects program errors leveraging detailed execution feedback, improving interpretability and accuracy.
Evaluations on six datasets demonstrate V Debugger's effectiveness, showing performance improvements of up to 3.2% in downstream task accuracy.
arXiv Detail & Related papers (2024-06-19T11:09:16Z) - JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing [12.338137154105034]
We investigate fuzzing for 7-Series and UltraScale(+) FPGA configuration engines.
Our goal is to examine the effectiveness of fuzzing to analyze and document the inner workings of FPGA configuration engines.
arXiv Detail & Related papers (2024-02-15T10:03:35Z) - VeriBug: An Attention-based Framework for Bug-Localization in Hardware
Designs [2.807347337531008]
In recent years, there has been an exponential growth in the size and complexity of System-on-Chip designs targeting different specialized applications.
The cost of an undetected bug in these systems is much higher than in traditional processor systems as it may imply the loss of property or life.
We propose VeriBug, which leverages recent advances in deep learning to accelerate debug at the Register-Transfer Level and generates explanations of likely root causes.
arXiv Detail & Related papers (2024-01-17T01:33:37Z) - DebugBench: Evaluating Debugging Capability of Large Language Models [80.73121177868357]
DebugBench is a benchmark for Large Language Models (LLMs)
It covers four major bug categories and 18 minor types in C++, Java, and Python.
We evaluate two commercial and four open-source models in a zero-shot scenario.
arXiv Detail & Related papers (2024-01-09T15:46:38Z) - Teaching Large Language Models to Self-Debug [62.424077000154945]
Large language models (LLMs) have achieved impressive performance on code generation.
We propose Self- Debugging, which teaches a large language model to debug its predicted program via few-shot demonstrations.
arXiv Detail & Related papers (2023-04-11T10:43:43Z) - HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on
FPGA Devices [71.45672882756001]
This study introduces a novel streaming architecture based toolflow for mapping 3D Convolutional Neural Networks onto FPGAs.
The HARFLOW3D toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics.
The ability of the toolflow to support a broad range of models and devices is shown through a number of experiments on various 3D CNN and FPGA system pairs.
arXiv Detail & Related papers (2023-03-30T08:25:27Z) - Detect-Localize-Repair: A Unified Framework for Learning to Debug with
CodeT5 [14.712753336831172]
We propose a novel unified emphDetect-Localize-Repair framework based on a pretrained programming language model CodeT5.
Our model significantly outperforms existing baselines from both NLP and software engineering domains.
arXiv Detail & Related papers (2022-11-27T16:11:29Z) - End-to-End Object Detection with Transformers [88.06357745922716]
We present a new method that views object detection as a direct set prediction problem.
Our approach streamlines the detection pipeline, effectively removing the need for many hand-designed components.
The main ingredients of the new framework, called DEtection TRansformer or DETR, are a set-based global loss.
arXiv Detail & Related papers (2020-05-26T17:06:38Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.