RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction

• URL: http://arxiv.org/abs/2503.21971v2
• Date: Tue, 29 Apr 2025 00:43:11 GMT
• Title: RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction
• Authors: Armin Abdollahi, Mehdi Kamal, Massoud Pedram,
• Abstract summary: We introduce a novel framework that leverages a 21k dataset of thoroughly cleaned and synthesizable Verilog modules.<n>We fine-tune CodeLlama using LoRA-based parameter-efficient methods, framing the task as a regression problem to accurately predict PPA metrics from Verilog code.
• Score: 4.825037489691159
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Large language models have recently transformed hardware design, yet bridging the gap between code synthesis and PPA (power, performance, and area) estimation remains a challenge. In this work, we introduce a novel framework that leverages a 21k dataset of thoroughly cleaned and synthesizable Verilog modules, each annotated with detailed power, delay, and area metrics. By employing chain-of-thought techniques, we automatically debug and curate this dataset to ensure high fidelity in downstream applications. We then fine-tune CodeLlama using LoRA-based parameter-efficient methods, framing the task as a regression problem to accurately predict PPA metrics from Verilog code. Furthermore, we augment our approach with a mixture-of-experts architecture-integrating both LoRA and an additional MLP expert layer-to further refine predictions. Experimental results demonstrate significant improvements: power estimation accuracy is enhanced by 5.9% at a 20% error threshold and by 7.2% at a 10% threshold, delay estimation improves by 5.1% and 3.9%, and area estimation sees gains of 4% and 7.9% for the 20% and 10% thresholds, respectively. Notably, the incorporation of the mixture-of-experts module contributes an additional 3--4% improvement across these tasks. Our results establish a new benchmark for PPA-aware Verilog generation, highlighting the effectiveness of our integrated dataset and modeling strategies for next-generation EDA workflows.

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