ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes

• URL: http://arxiv.org/abs/2504.07018v1
• Date: Wed, 09 Apr 2025 16:33:42 GMT
• Title: ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
• Authors: Amund Bergland Kvalsvik, Magnus Själander,
• Abstract summary: We present effective microarchitectures for two state-of-the-art secure schemes.<n>We find that the IPC impact of in-core secure schemes is higher than previously estimated.
• Score: 1.359473465752453
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Secure speculation schemes have shown great promise in the war against speculative side-channel attacks, and will be a key building block for developing secure, high-performance architectures moving forward. As the field matures, the need for rigorous microarchitectures, and corresponding performance and cost analysis, become critical for evaluating secure schemes and for enabling their future adoption. In ShadowBinding, we present effective microarchitectures for two state-of-the-art secure schemes, uncovering and mitigating fundamental microarchitectural limitations within the analyzed schemes, and provide important design characteristics. We uncover that Speculative Taint Tracking's (STT's) rename-based taint computation must be completed in a single cycle, creating an expensive dependency chain which greatly limits performance for wider processor cores. We also introduce a novel michroarchitectural approach for STT, named STT-Issue, which, by delaying the taint computation to the issue stage, eliminates the dependency chain, achieving better instructions per cycle (IPC), timing, area, and performance results. Through a comprehensive evaluation of our STT and Non-Speculative Data Access (NDA) microarchitectural designs on the RISC-V Berkeley Out-of-Order Machine, we find that the IPC impact of in-core secure schemes is higher than previously estimated, close to 20% for the highest performance core. With insights into timing from our RTL evaluation, the performance loss, created by the combined impact of IPC and timing, becomes even greater, at 35%, 27%, and 22% for STT-Rename, STT-Issue, and NDA, respectively. If these trends were to hold for leading processor core designs, the performance impact would be well over 30%, even for the best-performing scheme.

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