Running a six-qubit quantum circuit on a silicon spin qubit array

• URL: http://arxiv.org/abs/2505.19200v1
• Date: Sun, 25 May 2025 15:51:16 GMT
• Title: Running a six-qubit quantum circuit on a silicon spin qubit array
• Authors: I. Fernández de Fuentes, E. Raymenants, B. Undseth, O. Pietx-Casas, S. Philips M. Mądzik, S. L. de Snoo, S. V. Amitonov, L. Tryputen, A. T. Schmitz, A. Y. Matsuura, G. Scappucci, L. M. K. Vandersypen,
• Abstract summary: We implement a six qubit quantum circuit, the largest utilizing semiconductor quantum technology.<n>By programming the quantum processor, we execute quantum circuits across all permutations of three, four, five, and six neighbouring qubits.<n>Results reveal that, despite the high quality of individual units, errors quickly accumulate when combining all of them in a quantum circuit.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The simplicity of encoding a qubit in the state of a single electron spin and the potential for their integration into industry-standard microchips continue to drive the field of semiconductor-based quantum computing. However, after decades of progress, validating universal logic in these platforms has advanced little beyond first-principles demonstrations of meeting the DiVincenzo criteria. Case in point, and specifically for silicon-based quantum dots, three-qubit algorithms have been the upper limit to date, despite the availability of devices containing more qubits. In this work, we fully exploit the capacity of a spin-qubit array and implement a six qubit quantum circuit, the largest utilizing semiconductor quantum technology. By programming the quantum processor, we execute quantum circuits across all permutations of three, four, five, and six neighbouring qubits, demonstrating successful programmable multi-qubit operation throughout the array. The results reveal that, despite the high quality of individual units, errors quickly accumulate when combining all of them in a quantum circuit. This work highlights the necessity to minimize idling times through simultaneous operations, boost dephasing times, and consistently improve state preparation and measurement fidelities.

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