A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture

• URL: http://arxiv.org/abs/2506.17795v1
• Date: Sat, 21 Jun 2025 19:23:17 GMT
• Title: A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture
• Authors: Rachel Cazzola, Cyrus Minwalla, Calvin Chan, Jim Plusquellic,
• Abstract summary: We propose a unified PUF-TRNG architecture that leverages a combination of the static entropy available in a strong PUF.<n>A novel data postprocessing algorithm is proposed based on a modified duplex sponge construction.<n>Results indicate a stable and robust TRNG design with excellent min-entropy and a moderate data rate.
• Score: 0.0
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Hardware security primitives including True Random Number Generators (TRNG) and Physical Unclonable Functions (PUFs) are central components to establishing a root of trust in microelectronic systems. In this paper, we propose a unified PUF-TRNG architecture that leverages a combination of the static entropy available in a strong PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and the dynamic entropy associated with random noise present in path delay measurements. The SiRF PUF uses an engineered netlist containing a large number of paths as the source of static entropy, and a time-to-digital-converter (TDC) as a high-resolution, embedded instrument for measuring path delays, where measurement noise serves as the source of dynamic entropy. A novel data postprocessing algorithm is proposed based on a modified duplex sponge construction. The sponge function operates on soft data, i.e., fixed point data values, to add entropy to the ensuing random bit sequences and to increase the bit generation rate. A postprocessing algorithm for reproducing PUF-generated encryption keys is also used in the TRNG to protect against temperature voltage attacks designed to subvert the random characteristics in the bit sequences. The unified PUF-TRNG architecture is implemented across multiple instances of a ZYBO Z7-10 FPGA board and extensively tested with NIST SP 800-22, NIST SP 800-90B, AIS-31, and DieHarder test suites. Results indicate a stable and robust TRNG design with excellent min-entropy and a moderate data rate.

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