Average-computation benchmarking for local expectation values in digital quantum devices

• URL: http://arxiv.org/abs/2507.18708v1
• Date: Thu, 24 Jul 2025 18:00:27 GMT
• Title: Average-computation benchmarking for local expectation values in digital quantum devices
• Authors: Flavio Baccari, Pavel Kos, Georgios Styliaris,
• Abstract summary: We introduce a scheme that combines the target computation with variants of it, which, when averaged, allow for classically solvable correlation functions.<n>The variants exactly preserve the circuit architecture and depth, without simplifying the gates into a classically-simulable set.<n>We provide evidence that estimating average-computation expectation values requires running only a limited number of different circuit realizations.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: As quantum devices progress towards a quantum advantage regime, they become harder to benchmark. A particularly relevant challenge is to assess the quality of the whole computation, beyond testing the performance of each single operation. Here we introduce a scheme for this task that combines the target computation with variants of it, which, when averaged, allow for classically solvable correlation functions. Importantly, the variants exactly preserve the circuit architecture and depth, without simplifying the gates into a classically-simulable set. The method is based on replacing each gate by an ensemble of similar gates, which when averaged together form space-time channels [P. Kos and G. Styliaris, Quantum 7, 1020 (2023)]. We introduce explicit constructions for ensembles producing such channels, all applicable to arbitrary brickwork circuits, and provide a general recipe to find new ones through semidefinite programming. The resulting average computation retains important information about the original circuit and is able to detect noise beyond a Clifford benchmarking regime. Moreover, we provide evidence that estimating average-computation expectation values requires running only a limited number of different circuit realizations.

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