Lightweight Fault Detection Architecture for NTT on FPGA

• URL: http://arxiv.org/abs/2508.03062v1
• Date: Tue, 05 Aug 2025 04:23:50 GMT
• Title: Lightweight Fault Detection Architecture for NTT on FPGA
• Authors: Rourab Paul, Paresh Baidya, Krishnendu Guha,
• Abstract summary: Post-Quantum Cryptographic (PQC) algorithms are mathematically secure and resistant to quantum attacks.<n>They can still leak sensitive information in hardware implementations due to natural faults or intentional fault injections.<n>This research proposes a lightweight, efficient, recomputation-based fault detection module.
• Score: 0.8793721044482612
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Post-Quantum Cryptographic (PQC) algorithms are mathematically secure and resistant to quantum attacks but can still leak sensitive information in hardware implementations due to natural faults or intentional fault injections. The intent fault injection in side-channel attacks reduces the reliability of crypto implementation in future generation network security procesors. In this regard, this research proposes a lightweight, efficient, recomputation-based fault detection module implemented on a Field Programmable Gate Array (FPGA) for Number Theoretic Transform (NTT). The NTT is primarily composed of memory units and the Cooley-Tukey Butterfly Unit (CT-BU), a critical and computationally intensive hardware component essential for polynomial multiplication. NTT and polynomial multiplication are fundamental building blocks in many PQC algorithms, including Kyber, NTRU, Ring-LWE, and others. In this paper, we present a fault detection method called : Recomputation with a Modular Offset (REMO) for the logic blocks of the CT-BU using Montgomery Reduction and another method called Memory Rule Checkers for the memory components used within the NTT. The proposed fault detection framework sets a new benchmark by achieving high efficiency with significant low implementation cost. It occupies only 16 slices and a single DSP block, with a power consumption of just 3mW in Artix-7 FPGA. The REMO-based detection mechanism achieves a fault coverage of 87.2% to 100%, adaptable across various word sizes, fault bit counts, and fault injection modes. Similarly, the Memory Rule Checkers demonstrate robust performance, achieving 50.7% to 100% fault detection depending on and the nature of injected faults.

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