Efficient and Scalable Architectures for Multi-Level Superconducting Qubit Readout

• URL: http://arxiv.org/abs/2405.08982v2
• Date: Fri, 07 Mar 2025 22:25:33 GMT
• Title: Efficient and Scalable Architectures for Multi-Level Superconducting Qubit Readout
• Authors: Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu,
• Abstract summary: Many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace.<n>We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60times$ compared to the baseline.<n>Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a 6.6% improvement in readout accuracy over the baseline.
• Score: 0.8999666725996978
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Realizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60\times$ compared to the baseline while reducing readout time by 20\%, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a $100\times$ reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a 6.6\% relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward fault-tolerant quantum computing.

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